2045 年的芯片会是什么样？走进 Intel 工厂看技术与产能瓶颈

简要说明Brief Description

对英特尔晶圆厂的探访，以及对其技术领导层的采访，探讨了半导体工艺如何走向成熟，涵盖全环绕栅极晶体管、高数值孔径 EUV、钌互连、堆叠晶体管和混合键合。随后，讨论转向 AI 驱动的需求、设备瓶颈、晶圆代工经济学，以及重新思考制造工艺的可能性。A tour of Intel’s fabs and interviews with its technical leadership examine how semiconductor processes mature, from gate-all-around transistors and High-NA EUV to ruthenium wiring, stacked transistors, and hybrid bonding. The discussion then considers AI-driven demand, equipment bottlenecks, foundry economics, and possibilities for rethinking fabrication.

目录Table of Contents

• 简介
  Intro
• 英特尔如何启动新的工艺节点的研发部署
  How Intel brings up a new process node
• 英特尔从 10 纳米制程中吸取的经验教训
  What Intel learned from 10nm
• 从平面晶体管到环绕栅极晶体管
  From planar transistors to gate-all-around
• 为什么高数值孔径 EUV 对英特尔有利，却不适用于台积电
  Why High-NA EUV pays off for Intel but not TSMC
• 薯片的进化过程会不会截然不同？
  Could chips have evolved completely differently?
• 在英特尔的“热门话题”会议上
  Inside Intel's "Hot Topics" meeting
• 用钌替代铜线
  Replacing copper wires with ruthenium
• 为什么堆叠晶体管需要十年才能量产交付
  Why stacked transistors take a decade to ship
• 混合键合与芯片间瓶颈
  Hybrid bonding and the chip-to-chip bottleneck
• 目前没有足够的工具将芯片产量提高到十倍。
  There aren't enough tools to 10x chip production
• 英特尔能赶上台积电吗？
  Can Intel catch up to TSMC?
• Terafab，以及从头重新思考晶圆厂的设计
  Terafab, and rethinking the fab from scratch

简介Intro

人工智能带来的需求激增，是半导体行业有史以来遭遇过的最大冲击。人工智能正在推动计算需求大幅增长，需求轻而易举地超出了我们的最大产能 40% 到 50%，这在我过去从未见过。人工智能的进步一直由指数级增长的算力推动。要延续这一进步，像英特尔这样的晶圆厂就必须制造更多先进制程的计算芯片，既要提高芯片产量，也要提升每颗芯片的性能。但这些芯片的生产受制于英特尔从供应商那里采购的设备，最著名的就是 ASML 的 EUV 光刻机。没有这些设备，他们就无法在这里制造芯片。为了准备这次对英特尔管理层的采访，我花了两天时间参观英特尔的晶圆厂。我想了解制造全球最先进芯片需要什么，也想知道硬件将如何塑造人工智能的未来。There’s never been as big a shock to the semiconductor industry as the current surge in demand from AI. AI is driving incredible computing demand. Easily 40-50% above our maximum capacity, which I’ve never seen before. Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. But the production of these chips is bottlenecked by tools that Intel buys from their suppliers. Most famously, ASML’s EUV machines. If they don’t have the equipment, they can’t make the chips here. I spent two days touring Intel’s fabs to prepare for these interviews with its leadership. I wanted to understand what it takes to manufacture the world’s most advanced chips and how hardware is shaping the future of AI.

英特尔如何启用新的制程节点How Intel brings up a new process node

今天和我一起的是 Chris Auth，他负责开发目前已进入制造阶段的所有工艺。我想更具体地了解的是，新工艺的开发究竟是如何进行的。如果 14A 将在三年后或两年后推出，那么从现在到那时会发生些什么？我希望你尽可能详细地带我了解整个过程，从“良率是如何提升的？”到你们会查看哪些遥测数据、会进行哪些实验。我想尽可能具体地了解未来两年会发生什么。到目前为止，14A 已经开发了三年多，前期已经做了相当多的工作，才推进到现在这个阶段。目前，我们离工艺定型已经非常近了。I’m joined by Chris Auth, who leads development of all the processes that are currently under manufacturing. The thing I want to understand in more concrete detail is how the development of a new process actually happens. If 14A is going to come out in three years or two years from now, what is happening from now till then? I want you to walk me through as much detail as you can, everything from the level of “how is the yield improving?” to what kind of telemetry you guys look at? What kind of experiments do you guys run? I want to understand what is going to happen over the next two years as concretely as possible. 14A has been in development for about three-plus years at this stage, so quite a bit of pre-work has been done to get it to the stage that it’s at right now. Right now, we’re getting very close to where we’re finalizing the process.

我们正在敲定用于制造它的设备组，并对每一道工艺步骤进行微调。工厂里大约有 2,000 道工序需要完成。每一道工序都需要进行非常精细的操作，确保调整到位，能够投入制造，在这一工艺流程下每周处理数千片晶圆，而且每次都能稳定重复。现在，你们可能已经有了一定的良率。请详细讲讲良率是如何逐月提升的。现在有一条产线正在以 14A 工艺运行。从现在到下个月，会发生什么变化，从而使良率发生改变？你们如何找出缺陷所在？又如何修复？我们会持续开展缺陷识别工作，主要有两种方法。We’re finalizing the tool sets that it will be manufactured on, and we’re working on the fine-tuning of each of the process steps. There are about 2,000 steps in the factory that you have to go do. You need to do really intricate work at each one of those to make sure it’s fine-tuned, it can go into manufacturing, it can run thousands of wafers a week on this process, and it can be repeatable every single time. Right now, you might have a certain yield. Walk me through how that increases month over month. There’s a line running at 14A. What happens from now till next month that will result in the yield changing? How do you identify where the defects are? How do you fix that? There’s a constant process that we go through in identifying defects. There are two main ways that we’ll identify them.

一方面，我们有在线量测设备。这些设备会检查晶圆，并指出：“啊，这里有一个缺陷，那里有一个缺陷，这里还有一个缺陷。”此外，在生产线末端，我们会进行电气测试，或者进行分选，查看失效出现在什么位置。我们会识别出失效，然后对这些失效进行分析。我们会做截面分析。你昨天去过 TEM 实验室，也看到了如何获取截面图像。我们会对缺陷做截面分析，然后据此判断：“哦，这个缺陷位于这些层之间，所以一定来自工艺流程中的这个环节。哦，我们在这个环节有在线量测设备，它已经识别出了缺陷。这些就是我们需要着手处理的缺陷。”我们学到的是，在一个制程节点中不宜进行过多创新，因为创新越多，工艺就会变得越复杂。One is we have inline metrology. We have tools that will look at the wafers and say, “Ah, there’s a defect there, there’s a defect there, there’s a defect there.” Then also at the end of line, either electrical test or we sort and see where the fails are. We will identify failures, and then we will get analysis on those failures. We’ll cross-section it. You were in the TEM lab yesterday, and you saw how you can get cross-sections. You’ll get a cross-section of a defect, and from that, you’ll be able to say, “Oh, that defect is between these layers, so it must have come from this section of the flow. Oh, we have inline metrology in that section, which has identified defects. Those are the defects we need to go after.” What we’ve learned is that you don’t want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes.

英特尔从 10nm 制程中学到了什么What Intel learned from 10nm

虽然你能够让它正常运作，但你必须赶上特定的进度，而这正是客户最终想要的进度。拥有可预期的进度至关重要。你必须弄清楚，在客户要求的时间内满足其需求，自己能融入多少创新。英特尔在其 10 纳米制程节点的延误中，切身体会到了这种权衡的代价：该节点原定于 2016 年推出，却直到 2018 年才开始投产。通常，英特尔一直是摩尔定律的守护者，按照每两年推出一代制程的节奏推进，但他们最近一代产品的进度几乎推迟了四年。英特尔今天遭遇了四个月来最糟糕的一天，股价目前下跌超过 15%。我还想指出，台湾半导体因英特尔的坏消息而上涨了 13%。你能谈谈你认为英特尔从 10 纳米制程中吸取了哪些教训吗？10 纳米制程就是一个很好的例子，当时我们的目标定得非常激进。我们当时采用了所谓的“超缩放”策略，也就是说，我们的缩放速度远超以往的做法。为了做到这一点，我们提出了各种创新方案，设法在不使用新设备的情况下实现目标，因为当时新设备还没有准备好。While you’ll be able to get that to work, you need to hit a certain schedule, and that’s the schedule that your customer ultimately wants. Having that predictable schedule is a key piece. You’ve got to figure out how much innovation you can put in order to meet the customer’s requirements in the timeline that they need it. Intel learned how costly that tradeoff can be with delays to its 10 nanometer node, whose original target launch date was 2016, but which didn’t begin manufacturing until 2018. Usually Intel has been the keeper of Moore’s Law, a new cadence of manufacturing every two years, but their last set of products slipped almost four years. Intel today having its worst day in four months, the stock now down more than 15%. I also want to point out Taiwan Semiconductor up 13% off of Intel’s bad news. Walk me through what lessons you think Intel has learned from 10 nanometer. Ten nanometer was a good example of where we had very aggressive targets. We were doing what was called hyperscaling at the time, so we were scaling much faster than what had been historically done. In order to do that, we came up with all sorts of innovative ideas on how we could achieve that without new tools, because the tools weren’t ready.

这给工艺流程带来了很大负担，也给工程师们带来了很大压力。归根结底，10 纳米是一项很棒的技术：它的良率、性能和成本都达到了世界一流水平，但研发所花的时间比我们希望的更长。因此，我们努力把这些经验运用到未来的技术节点上，并表示：“我们需要限制其中引入的创新规模，确保进度不受影响。”你认为，最应该留到未来版本中的技术是什么？大概就是 EUV 了。我们开始制定 10 纳米工艺方案时，得出的结论是 EUV 尚未成熟。EUV 是极紫外光刻的简称。它利用波长为 13.5 纳米的光来刻印芯片图案，这一波长约比芯片制造商此前依赖的光刻设备所使用的光短 14 倍。That put a lot of burden on the process and a lot of burden on the engineers. Now, at the end of the day, 10 nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost, but it took us longer to do that than what we would have liked. So we’ve tried to take that learning into future technology nodes and say, “Hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule.” What do you think was the main technology that should’ve been saved for a future version? EUV was probably the big thing. When we started to define 10 nanometer, the conclusion was EUV was not ready. EUV is extreme ultraviolet lithography. It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chipmakers had relied on.

波长越短，单次曝光能够印制的特征就越精细。但英特尔认为，这项技术无法及时就绪。台积电则早得多就转向了 EUV。它在 2019 年将 EUV 用于大规模量产，并于 2020 年在 5 纳米节点上进一步扩大应用。英特尔首个 EUV 工艺直到 2023 年才应用于产品，因此台积电在这些设备上的经验大约多了四年。昨天，我们去了研究实验室，提前了解了二维材料、CFET 和钌互连技术。我很好奇，你们如何判断这些技术是否成熟到足以用于下一代节点？10 纳米工艺还带来了一项成果：我们开始制定一套成熟度指标。我们会在一个称为“阶段关卡”的流程中使用这些指标，并据此规定：“从技术探索进入开发阶段，需要达到以下标准。”The shorter the wavelength, the finer the features that a single exposure can print. But Intel decided this technology wasn’t going to be ready in time. TSMC transitioned to EUV much sooner. It put EUV into volume manufacturing in 2019 and ramped it up further on its 5nm node in 2020. Intel’s first EUV process did not reach products until 2023, so TSMC had about four more years of experience with these machines. Yesterday, we were at the research lab getting a preview of 2D materials and CFET and ruthenium interconnects. I’m curious about how you decide whether that technology is mature enough for the next node. One thing that did also come out of 10 nanometer is we started to define a set of maturity metrics. We use those maturity metrics in a process which we call phase gate, where we would say, “To go from pathfinding into development, these are the criteria that we need to go hit.”

从平面晶体管到环绕栅极晶体管From planar transistors to gate-all-around

我们有良率标准、缺陷标准和性能标准，必须达到这些标准，才能进入流程的下一阶段。如果有哪项达不到标准，就无法通过这一关，而会转向下一种技术。我们专注于那些已经准备就绪、可以运行并投入工艺的项目，因为按计划推进是关键之一。要按计划推进并不容易，部分原因是新型晶体管设计需要数十年才能成熟。现代芯片中的晶体管从 1960 年展示的平面 MOS 晶体管演变而来。此后，晶体管的发展历程就是从二维走向三维的过程。Chris 接下来要介绍的每一项发展，从 FinFET 到环绕栅极，都是这一演进过程中的一步。因此，我们先来了解一下基本晶体管，以及它的各个部分随着时间发生了怎样的变化。晶体管本质上是一种开关。开关打开时，电流可以在它的两端之间流动，这两端称为源极和漏极。在源极与漏极之间的硅上方，有一个称为栅极的部分。给栅极施加正电压就会打开开关，因为正电压会将下方硅中的带负电电子向上吸引到栅极附近。There are yield criteria, defect criteria, performance criteria, and we need to hit those in order to move to the next set of the flow. If there’s something that doesn’t make that, then it misses that, and it goes on to the next technology. We focus on the items that are ready and we can run and put into a process, because one of the key things is staying on schedule. Staying on schedule is hard partly because new transistor designs take decades to mature. Modern chip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history of transistors since has been the progression from two dimensions into three. Each development that Chris goes on to describe, from FinFET to gate-all-around, is a step in that progression. So it’ll help to first look at a basic transistor and how its parts have changed over time. A transistor is basically a switch. When it’s turned on, it allows current to flow between its two ends, which are called the source and the drain. A piece called a gate sits on top of the silicon between the source and the drain. Applying a positive voltage to the gate turns the switch on, because the positive voltage pulls negatively charged electrons in the silicon beneath up toward the gate.

不过，一层很薄的绝缘层阻止电子真正到达栅极。因此，电子会聚集在绝缘层下方，形成一条从源极通向漏极的狭窄导电通路。这被称为沟道。移除电压后，电子便会散开，沟道消失，开关随之关闭。随着晶体管不断缩小，源极和漏极变得非常接近，即使开关本应处于关闭状态，电流也能通过沟道流动。我们需要一种更好的方法来控制沟道，防止电流泄漏。解决办法是让栅极从更多侧面接触沟道，从而更紧密地控制它。在最初的平面晶体管中，栅极只从上方接触沟道。FinFET 晶体管则将沟道挤压成一片由硅制成的垂直薄鳍。However, a thin layer of insulation stops them from actually reaching the gate. So the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain. This is called the channel. Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off. As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off. We needed a better way to control the channel and prevent current from leaking through. The fix was to give the gate a tighter grip on the channel by touching it from more sides. In the original planar transistor, the gate only touches the channel from the top. The FinFET transistor squeezes the channel into a thin vertical fin of silicon.

栅极覆盖在鳍片上，因此可以从三个侧面控制沟道。接下来的发展是在覆盖沟道顶部和侧面的基础上，进一步覆盖其底部。这项技术称为环绕栅极（gate-all-around），它将沟道切分成一条条薄带，每条薄带都被栅极完全包裹。但要实现环绕栅极，需要采用新材料和新的制造工艺。要制造这些悬空的硅带，首先要将它们夹在交替堆叠的临时占位材料层之间，这些材料会占据栅极最终形成的位置。之所以使用占位材料，是因为真正的栅极材料无法承受后续的加工过程，其中包括将晶圆加热至约 1,000 摄氏度。完成这些高温工序后，芯片制造商会蚀刻掉占位材料，使硅带悬空。The gate drapes over the fin, so it controls the channel from three sides. The next progression from there was to cover not only the top and the sides of the channel, but also the bottom. This technology is called gate-all-around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate. But getting gate-all-around to work required new materials and new manufacturing steps. To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material, which holds the space where the gate will eventually go. We use a placeholder because the materials in the real gate wouldn’t survive the processing that comes after, which involves baking the wafer at around 1,000 degrees Celsius. Once these hot steps are done, chipmakers etch away the placeholder, leaving the ribbons suspended.

然后，他们用一种叫作高介电常数材料（high-k material）的特殊绝缘体薄薄地填满每条带状结构周围的空隙，目的是让栅极对沟道的控制力更强。接着，他们在这种材料上方放置栅极本身的金属。FinFET 于 1989 年在实验室中得到演示，并于 2011 年在英特尔实现大规模量产。全环绕栅极晶体管则早在 1988 年就已得到演示，但三星直到 2022 年才开始生产全环绕栅极芯片。因此，FinFET 和全环绕栅极这两种技术大约在同一时期研发出来，却相隔十年才实现量产。我想问问 Chris，为什么要花这么长时间才能发展到如今的全环绕栅极技术。你能不能带我梳理一下迈向大规模量产的过程？我想具体了解，当你有了一个想法，比如“嘿，我们要把沟道做得更小，再把它包围起来……”之后，会发生什么。Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-k material, whose purpose is to let the gate pull more strongly on the channel. And then on top of this material, they put the metal of the gate itself. FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011. A gate-all-around transistor had been demonstrated a year earlier, in 1988, but Samsung didn’t begin producing gate-all-around chips until 2022. So these ideas, FinFET and gate-all-around, were developed around the same time, but they reached production a decade apart. I wanted to ask Chris why it took so long to get to this current gate-all-around technology. Maybe you can walk me through the process of getting into high-volume manufacturing. I want to understand concretely, once you have an idea that, “Hey, we’re going to make the channel smaller, we’re going to surround it…”

材料科学中的所有其他问题——比如如何避免破坏栅极——究竟是怎么解决的？为什么要花这么长时间？全环绕栅极就是个很好的例子，因为早在 90 年代，我们就知道有这个想法。但我们也知道，要将它应用于大规模量产，会遇到这些问题。与此同时，还有高介电常数金属栅等其他技术，还有应变硅，还有已经问世的 FinFET。问题在于，什么时候才是着手解决这些问题的恰当时机？嗯，你不会想在不得不解决之前就着手解决。如果还有其他技术可以提升性能，你就会先采用那些技术。所以我们沿着这条路走了下来。我们采用了应变硅、高介电常数金属栅，也采用了 FinFET，后来就变成了：“嗯，我们需要进一步推进。”All the other problems of material science, figuring out how to not destroy the gate, how do they actually get figured out? Why does it take so long? Gate-all-around’s a good example, because back in the ’90s we knew of this idea. But we knew there were going to be these problems on how you put this into high-volume manufacturing. At the same time, there are other things like high-K metal gate. There’s strained silicon, there’s FinFETs that are out there. It’s a question of when’s the right time to go and tackle those? Well, you don’t want to tackle something before you have to. If you have these other things that can drive performance, you would go and do that. So we went through this path. We did strained silicon, high-K metal gate, we did FinFETs, and then it became, “Well, we need to do things further.

我们怎样才能做到这一点？”嗯，环绕栅确实是终极晶体管。也许是时候着手解决你遇到的一些问题了。你说得对，现在你得考虑如何将高K金属栅应用于环绕栅结构。这种创新需要时间。有时候你需要新材料；有时候你需要不同的设备，才能完成你需要做的一些事情，而这就需要设备供应商进行发明创新。你得去找设备供应商说：“嘿，我需要一种能做 XYZ 的设备。我需要一种能够沉积特定材料的气体，用来构成其中的结构。我需要一个具备这种特性的加热卡盘。”所有这些都需要时间。有些过程是迭代式的：你得先制造一个环绕栅晶体管，然后说：“哦，嗯，这行不通。How do we get there?” Well, gate-all-around’s really the ultimate transistor out there. Maybe it’s time to go and start tackling some of those issues that you have. You’re right, now you have to look at how do you put high-K metal gate in with gate-all-around. It’s that innovation that takes time. Sometimes you need new materials. Sometimes you need a different tool in order to be able to do some of the things that you need to go do, and that requires invention from the tool vendors. You have to go to the tool vendor and say, “Hey, I need a tool that can do XYZ. I need a gas that can deposit this particular material that goes into that. I need a heating chuck that has this characteristic to it.” All those things take time. Some of it’s iterative, where you have to run a gate-all-around transistor and say, “Oh, well, that didn’t work.

“让我弄清楚我的假设哪里出了问题，再换一种结构试试。”从研发的本质来看，从那个只需不断缩小平面晶体管、并从丹纳德缩放中获益的时代，到我们今天所处的世界，发生了怎样的变化？研发过程是不是已经完全不同了？过去的思路是：“让东西变得越来越小。”如今，你会同时关注性能的其他诸多方面，而尺寸上的改进也不再那么容易实现。请跟我讲讲，研发过程在那个阶段是否发生了某种关键变化。回顾20世纪80年代和90年代，没错，当时的发展确实主要由丹纳德缩放和光刻技术推动。我们只要不断缩小器件，晶体管就会变得更快、更可靠，而且发展节奏非常可预测。Let me figure out what was wrong with my hypothesis and try it again with some different structure.” How has the nature of R&D changed from the era of just making planar transistors smaller and smaller and getting the benefits of Dennard scaling, to the world we’re in today? Is it just a totally different kind of R&D process? Previously it was, “Let’s make things smaller, smaller, smaller.” Now you look at all these other facets of performance at the same time, and improvements in size don’t come as easily. Walk me through whether there was some crucial change in the R&D process at that point. If you look at the ’80s and ’90s, yes, it was driven really by Dennard scaling, lithography. We just made things smaller, transistors got faster, they got more reliable, and it was a very predictable cadence.

进入21世纪后，我们意识到：“这样已经不够了。我们得做些不一样的事。”对我来说，这成了创新的黄金时代。每推进一个技术节点，你要怎样实现更高的集成度？怎样提升性能？这推动了应变硅、高介电常数金属栅、FinFET、全环绕栅以及背面供电等技术的发展。在80年代和90年代，人们会觉得这些技术“噢，不行，我们不会碰这些”，因为我们一直沿用同一套工艺流程，只是不停地缩小、缩小、再缩小。但对我这样痴迷于晶体管的人来说，这简直太棒了，因为如今可用的技术路线图已经全面开放。你可以尝试各种各样的方法，也可以引入新材料。只要看看我们90年代使用的材料数量，再对比一下今天用的材料，就能明白这一点。When we started to hit the 2000s, we saw, “That’s not good enough anymore. We need to do something different.” To me, it became this golden age of innovation. For each technology node, how are you going to provide more scaling? How are you going to provide more performance? It drove things like strained silicon. It drove high-K metal gate. It drove FinFETs. It drove gate-all-around. It drove backside power. These are things that in the ’80s and ’90s you would be like, “Oh no, we’re not touching any of that,” because we just continued to have the same process flow. We just scaled it, scaled it, scaled it. But for somebody like me who’s a transistor junkie, it’s awesome, because now the playbook’s open. You can do all sorts of things out there. You can bring in new materials. Just look at the number of materials we used to use in the ’90s versus the materials today.

为什么高 NA EUV 对英特尔物有所值，对台积电却不然Why High-NA EUV pays off for Intel but not TSMC

这很可能已经增长了 10 倍。创新层出不穷，比如原子层沉积。你可以逐个原子地控制这些东西。因此，你处理这一工艺的方式发生了很大变化。以前的做法是：“尽量什么都别改。”现在则是：“抡起大锤，把它拆开，然后想出一些新点子。”在 14A 制程中，英特尔使用一种新型光刻设备：高数值孔径 EUV。它使用的极紫外光与现有 EUV 设备相同，但光学系统有所不同。NA，即数值孔径，是衡量设备的反射镜能将多宽的光锥聚焦到晶圆上的指标。能够聚焦的光锥越宽，光线就能刻蚀出越小的点。标准 EUV 设备的 NA 为 0.33，而高数值孔径设备将其提高到了 0.55。因此，高数值孔径设备单次曝光就能印制出尺寸小约 1.7 倍的特征。当特征尺寸小于光刻设备所能印制的尺寸时，芯片制造商就必须将图案拆分成多次曝光，每次印制一组不同的特征。最密集的图案可能需要两次、三次，甚至四次曝光。每增加一次曝光，都会占用这台价值约 2 亿美元的设备宝贵的运行时间，同时也多一次产生缺陷的机会。It’s probably gone up 10X. There’s a lot of innovation. There’s atomic layer deposition. You’re controlling this stuff atom by atom. So it’s changed a lot how you approach the process. Before, it was, “Try to not change anything.” Now it’s, “Take the sledgehammer and start tearing the thing up and come up with some new idea.” For 14A, Intel is using a new kind of lithography machine: High-NA EUV. It uses the same extreme ultraviolet light as today’s EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how wide a cone of light the machine’s mirrors can focus onto the wafer. The wider the cone you can focus, the smaller the spot that your light can carve. Standard EUV machines have an NA of 0.33. High-NA widens it to 0.55. So High-NA can print features about 1.7 times smaller in a single pass. When features are smaller than the lithography machine can print, chipmakers have to split the pattern across several passes, each printing a different set of features. The most tightly packed patterns can require two, three, or even four passes. Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects.

High-NA设备的成本大约是普通设备的两倍，但可以减少所需的曝光次数。因此，决定它们是否值得更高价格的问题在于：它们能节省多少时间，又能在多大程度上降低缺陷风险。你们现在在14A节点使用High-NA EUV设备，而TSMC表示，对他们来说这类设备目前还不具备经济性。你们如何判断下一台光刻设备是否已经到了可以采用的时候？ High-NA就是一个很好的例子。由于我们的技术架构与TSMC不同，面对同一套设备，我们会得出不同的结论。我们采用背面供电，这意味着你们可以放宽一些正面的间距要求，从而能够直接用High-NA进行曝光。TSMC没有背面供电，因此必须采用更紧密的间距，而High-NA无法做到这一点，所以他们不得不使用EUV双重图形化。High-NA machines cost about twice as much, but they can reduce the number of passes that are needed. So the question which determines whether they justify their higher price is how much more time they save and how much they reduce the risk of defects. Now you guys are using High-NA EUV tools for 14A, whereas TSMC has said that they don’t make economic sense yet for them. How do you decide whether the next litho tool is the one that is ready to adopt or not? High-NA’s a good example of where, because of the architecture of our technology versus TSMC’s, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side. That allows you to print that directly with High-NA. TSMC has to run tighter pitches because they don’t have backside power, and they can’t do that with High-NA, so they have to use double patterning EUV.

所以对他们来说，这并没有太大帮助；但对我们来说，帮助很大。到了 14A，我们把它保留为一个选项，之后会和客户讨论，因为它有一定的价值，同时也会增加一些复杂性。Chris 指的是一项名为背面供电的技术。芯片上有两种不同的布线：电源线向晶体管输送电力，因此需要做得较粗；信号线则让晶体管彼此通信。信号线要细得多，但彼此之间需要留出间距，以免一根线的信号干扰另一根线的信号。过去，所有这些电源线和信号线都必须挤在晶体管上方。英特尔最新的制程将电源线移到了晶体管下方，也就是晶圆背面。So for them, it’s not very helpful. For us, it is very helpful. Now at 14A, we’ve left it as an option, and it’s something that we’ll have a discussion with the customer on, because there’s some value proposition to it, and there’s some complexity that it adds. Chris is referring to a feature called backside power. A chip has two different kinds of wiring. Power lines deliver electricity to the transistors, and they need to be thick. Signal lines let the transistors talk to each other. They’re much thinner, but they need to be spaced apart so that the signal from one wire doesn’t interfere with the signal from another. In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel’s newest process moves these power lines below the transistors, to the back of the wafer.

这能腾出顶部空间，因此信号线不必排得那么密。这项改动让高数值孔径光刻对英特尔来说变得值得采用。没有背面供电，布线会非常密集，即使使用高数值孔径光刻，也需要多次曝光才能完成。采用背面供电后，一次高数值孔径曝光就足够了。现在，外部公司可以委托英特尔制造自己设计的芯片。它们遵循英特尔的工艺设计套件（PDK）：其中列出了特定工艺能够制造什么，以及制造时必须遵守的规则。对于计划基于 14A 开发产品的客户，你们现在就需要把这项技术纳入 PDK 吗？ 现在的 PDK 中已经提供了这一选项。我们会与每位客户分别讨论，了解他们是否想采用这条路线。关于 18A，公开报道曾指出，PDK 出现延迟或问题，以至于某些指令无法正常工作，导致人们难以利用你们的代工服务来制造芯片。This frees up space on top, so the signal lines don’t have to be packed as tightly. This change makes High-NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with High-NA. With backside power, a single High-NA pass is enough. Outside companies can now commission Intel to manufacture chips that they’ve designed. They follow Intel’s process design kit, or PDK: the menu of what a given process can build, and the rules for building it. Do you need to lock that into your PDK right now for customers who are planning on developing on 14A? It’s an option in the PDK today, and we’re handling it as a customer-by-customer discussion as to whether or not they want to go down that path or not. For 18A, there was public reporting that there were delays in or issues with the PDK, such that some instructions didn’t work, and it was difficult for people to use your foundry to build their chips.

请谈谈英特尔转型为代工厂的过程，以及如何建立一套 PDK，让其他客户也能用它来制造各自要做的芯片。成为代工厂确实需要经历一个学习过程，我们的竞争对手也走过这条路。PDK 就是一个很好的例子。几十年来，我们一直是 IDM。我们会向产品团队展示晶体管数据，并与他们来回共享这些数据，但没有正式的 PDK 流程。因此，我们必须在 18A 上实施这一套新流程。18A 刚开始时还没有 PDK。客户就 PDK 的质量和成熟度，以及他们希望其中包含哪些信息，给了我们很多反馈。我们努力将这些反馈纳入其中，确保 PDK 满足客户的要求。Tell me about the process of Intel becoming a foundry and then having a PDK that other customers can use to make whatever chip they’re making as well. There’s definitely a learning curve to how you become a foundry. That’s something that our competitors have gone through as well. PDK is a good example of that. For decades, we’ve been an IDM. We’ve gone to our product teams and shown them our transistor data, and we share that data back and forth, and we haven’t had a formal PDK-type process. So that’s a new process that we’ve had to implement on 18A. 18A started out not having a PDK. There’s definitely a lot of feedback we’ve gotten from the customers as to what they expect for quality and maturity of the PDK and what sort of information they want to see in there. We’ve tried to incorporate that into making sure that we have a PDK that meets our customers’ requirements.

这就是我们最终走到的阶段。我们开始拿到具备这些特性的 PDK，而 14A 从一开始就会具备这些特性。它的 PDK 质量非常高。再说一次，针对 PDK 0.5、0.9 和 1.0，各自都有成熟度指标。我们不断收集客户反馈，并将其融入 PDK 的质量改进中。在英特尔的大部分发展历程中，其晶圆厂只生产英特尔自己的芯片。这或许是台积电得以取得优势的原因之一。服务众多客户，让台积电有更多晶圆可供学习，有更多收入可以再投资，也面临更大的按时交付压力。基本上，所有企业客户都有一套共同的产品要求；你必须满足这些要求，才能开始谈合作。这些要求包括 SSO，让员工可以使用公司的账户登录你的应用；还包括目录同步，这样有人离职时，系统就会自动撤销其访问权限。That’s where we’ve ended up. We’re starting to get PDKs that have this, and 14A will have that from the get-go. It has very high quality PDKs. Again, there are maturity metrics for what is a PDK 0.5 versus a 0.9 versus a 1.0. We’re constantly going through and taking customer feedback and incorporating that into the quality of our PDK. For most of its history, Intel’s fabs made only Intel’s chips. That could be part of what allowed TSMC to gain an edge. Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines. Basically, all enterprise customers have a shared set of product requirements that you have to meet if you want to even start talking about doing business with them. These are things like SSO, so employees can log into your app with their company accounts, or directory sync, so that whenever someone leaves, their access gets shut off automatically.

这些功能比你想象的更难做好，而自行开发的风险收益比也确实不太划算：SSO 做得稍微好一点，大概不会推动业务增长；但如果做坏了，肯定会拖累增长。WorkOS 让你能够使用经过实战检验的各类常见企业功能，例如 SSO、SCIM、RBAC、审计日志等。WorkOS 还提供专为智能体打造的这些功能，让它们能够登录、获取适当的权限，并在你的产品中执行操作。只需几行代码，就能接入所有这些功能，让你快速上手并开始向企业客户销售。OpenAI、Anthropic 和 Thinking Machines，以及其他 3,000 多家公司，都依赖 WorkOS 来满足其企业级需求。These features are harder to get right than you think, and the risk-reward for building them in-house doesn’t really make sense: a slightly better version of SSO probably won’t accelerate your growth, but a broken one will definitely stunt it. WorkOS gives you access to battle-tested versions of all the most common enterprise features—things like SSO, SCIM, RBAC, audit logs, and more. WorkOS also has versions of these features that are purpose-built for agents, so they can log in, grab the right permissions, and take actions within your product. All of these features can be plugged in with just a few lines of code, so you can add them and get started selling to enterprises. OpenAI, Anthropic, and Thinking Machines—as well as more than 3,000 other companies—all rely on WorkOS to meet their enterprise requirements.

如果你想加入他们，请访问 workos.com，并告诉他们是我推荐你去的。If you want to join them, go to workos.com and tell them that I sent you.

薯片是否可能以完全不同的方式演化？Could chips have evolved completely differently?

如果说在60年代有只蝴蝶扇动了翅膀，你能想象这样一个世界吗：人们甚至没听说过“全环绕栅”这个词，也不熟悉这个概念，而是走上了科技树上截然不同的一条分支？你觉得科技树往下发展到多深的地方，情况才可能彻底不同？有没有可能我们甚至不用铜？比如说晶体管和互连技术，看看我们如今发展到的程度——晶体管、全环绕栅，以及它作为理想晶体管结构的地位，在某种程度上都是必然的。正如我所说，早在90年代，我们就已经在讨论这类技术了。背面供电就相当超前了。即使在90年代，要把整个硅衬底去掉、再在背面布线的想法，也可能有点超前。If a butterfly flapped its wings in the ’60s, could you imagine a world where gate-all-around is not even a word people have heard of, an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree? How far down the tech tree do you think things could be totally different? Could it be that we’re not even using copper? If you look at, say, transistors and interconnects, where we’ve gotten to, as far as the transistor and gate-all-around and it being the ideal transistor structure, was somewhat inevitable. As I said, in the ’90s we were already talking about these types of things. Backside power, that one’s pretty out there. Even in the ’90s, the idea that you’re going to strip off the entire silicon substrate and put lines on the backside, that one is probably something that’s a little bit out there.

铜，当然铜线是最好的，所以我不知道你们怎么会选择铜以外的材料。不过你们也在探索其他材料——对于间距最小的那些互连，换掉铜是不可避免的。这就是一个很好的例子：届时会有另一种材料加入进来。但对于间距较大的线路，我觉得铜基本上就是最佳选择了。一旦开始采用全环绕栅晶体管和背面供电，就进入了一个截然不同的领域。你会发现，情况不再是“嘿，下面有个衬底，然后把所有东西都堆在上面”。现在，晶体管悬置在互连结构中，于是你就会想：“好吧，那为什么不把晶体管、互连结构、再多加一些晶体管、再加更多互连结构这样一层层叠起来呢？”我们现在用彼此堆叠的独立芯片来实现的，就是这种3D堆叠。Copper, of course copper wires are the best, so I don’t know how you would end up somewhere else besides copper. But you guys are exploring other— For some of the very tightest pitches, it’s inevitable that you will replace copper. That’s a good example of where you will have another material that will come in there. But for the larger lines, I think copper is about where it’s at. Once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime. Now you see it’s not, “Hey, there’s just some substrate and you stack everything on top.” Now you’ve got a transistor which is floating in interconnect, and you’re like, “Okay, well, why don’t I have transistors, interconnect, a little more transistors, more interconnect?” This whole 3D stacking that we now do with just discrete chips that we stack on top of each other.

这时你会想：“为什么我不能就这样构建一个完整的结构呢？”你在存储器、NAND、DRAM领域都能看到这种情况。它们有一些令人惊叹的三维结构。NAND已经这么做了，DRAM也在探讨这件事，但我认为DRAM最终也必然会走到这一步。很多人会说：“哦，不，我们不会这么做，因为未来五年内做不到。”拜托，咱们把时间尺度放大一些。把时间放到10年、20年。到了2045年，你觉得能做到吗？这时你就会开始说：“哦，对，我能想象到那时我们会有一些相当新奇的结构。”我们总是受限于自己认为未来四年内可能实现的东西。正如我一直说的，每当有人问“你怎么看技术的演进方向？”时，我们能看清的也就大约四年。等这四年过去，你又会说：“嗯，我觉得再往后四年，我们还能在此基础上做出一些东西。”Now you’re like, “Why can’t I just build an entire structure like this?” You see it with memory, NAND, DRAM. They have some incredible 3D structures. NAND already does it, DRAM talks about it, but I think that DRAM inevitably is going to go there too. A lot of people say, “Oh no, we’re not going to do this because we can’t do it in the next five years.” Well, come on, let’s put a larger timescale on this. Let’s put 10 years, 20 years. In 2045, do you think you could do it? Now you start to say, “Oh yeah, I could see us having some pretty exotic structures at that point.” We limit ourselves by what we see as possible in the next four years. As I’ve always said, when people say, “How do you see technology scaling going?”, we have visibility for about four years. Then you get out to the four years, and you go, “Yeah, I think there’s something we can do another four years out of that.”

等到四年后，你就会觉得：“嗯，我认为还是能做出点什么的。”但如果把时间拉到十年，就很难说未来会是什么样了。克里斯提出的向上堆叠的想法，可以从晶体管本身入手。芯片使用两种晶体管，称为 n 型和 p 型，它们的工作方式相同，只是电荷相反。几乎所有电路都是将这两种晶体管配对构成的。如今，芯片制造商把它们并排制造。下一步是将它们直接上下堆叠，以节省空间。原则上，这样能在相同面积内容纳两倍数量的晶体管。这种设计称为 CFET，是互补场效应晶体管（complementary field-effect transistor）的简称。但每增加一层，都会增加制造工序和成本，还会导致热量积聚，而且没有明确的散热途径。And you get to that four years, and you’re like, “Yeah, I think you can do something.” But if you start to talk about 10 years, it becomes hard to say what it’s going to be. Chris’s idea of building upward could start with the transistors themselves. Chips use two types of transistor, called n-type and p-type, which work the same way, but with the charges reversed. Nearly every circuit is built by pairing them up. Today, chipmakers build them side by side. The next step is to stack them directly on top of each other in order to save space. In principle, that fits twice as many transistors into the same area. This design is called a CFET, short for complementary field-effect transistor. But every extra layer adds manufacturing steps and cost, and also leads to heat building up that doesn’t have a clear way to escape.

由于逻辑电路比存储器消耗更多功耗，所以像堆叠 DRAM 来制造 HBM 或 3D NAND 那样，用逻辑电路进行堆叠就没那么容易，因为存在散热问题。从长远来看，这是不是根本性的问题？怎么说呢——热管理。谈到“是什么限制了计算能力”，有三个方面。第一，开关速度有多快，也就是器件的工作频率。第二，完成一次开关需要消耗多少功率，也就是功耗效率。第三，如何散掉开关过程中产生的热量？这就是热管理的问题。这些都不是什么新问题。回溯 20 年，你就能找到讨论这三方面的文章。问题在于热管理……尤其是当你开始谈论这类 3D 器件时，要如何应对？Because logic consumes more power than memory, you can’t do stacks of DRAM that make HBM or 3D NAND as easily with logic, because of the heat issue. Is that the fundamental issue over the long run? How you— Thermals. There are three things you have when you try to say, “Hey, what limits compute?” It’s how fast can you do the switch, so the frequency of the device. How much power does it take in order to do that switch, so the power efficiency of it. The third one is, how do you dissipate the heat that was generated by doing that switch? That’s the thermals piece of it. These are not new problems. You can go back 20 years and you can see articles on these three things. The question is, thermals… how do you deal with that, particularly when you start to talk about these 3D-type devices?

在英特尔的“热门话题”会议中Inside Intel's "Hot Topics" meeting

我们需要这类系统级分析和仿真工具。我认为我们还处于起步阶段，因为我们刚刚开始研究这个问题。它是一个瓶颈，而且还会继续成为瓶颈；不过话说回来，这些问题都是我们可以着手解决的。只要投入工作，这些问题就能得到改善，但工程时间有限，供实验使用的晶圆也有限。在成千上万个问题中决定资源该投向哪里，本身就是推动一个制程节点进入量产阶段时最困难的环节之一。 我旁听了英特尔的一场 Hot Topics 会议，会上大家会做出这些决定。我现在和 Kevin Fischer 在一起。今天上午的 Hot Topics 会议上，他主持会议时立下了规矩，你们当时正在讨论如何改进 18A 和 18A-P 技术。有人会带来他们正在进行的各种实验、关于如何提升良率和性能的各种想法，然后你和你的整合工程师会告诉他们需要哪些数据、应该如何推进，以及你们认为怎样才能加快进度。我想让大家了解这些会议中的文化氛围。有一点让我印象很深：这正成为你们最先进制程节点的瓶颈。There is a need for that sort of system-level analysis and simulation tools. I think we’re in its infancy because we’ve just started to look at this. It is a limiter, and it will be a limiter, but again, these are problems that we can go solve. The problems respond to work, but engineering time is finite, and so are the wafers for experiments. Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node. I sat in on one of Intel’s Hot Topics meetings, where those decisions get made. I’m here with Kevin Fischer, who was laying down the law this morning at the Hot Topics meeting, where you guys were discussing how you’re improving 18A and 18A-P technologies. People would come to you with different experiments they were running, different ideas they had for improving yield and performance, and then you and your integration engineers would tell them what data you needed, how they should proceed, how you think they could move things faster. I want people to have a sense of the culture at these meetings. One thing I found striking is that this is bottlenecking your most advanced node.

你希望进展快一些，所以会有点强硬地推进。我想说，普通工程师并不了解这件事的利害关系和紧迫性，也不清楚它会如何影响英特尔的利润，或影响我们的客户。他们对这些问题完全没有了解。他们通常会设定一套自己想要收集的数据标准。他们会碰到这样的界限：“我提出了要求，有人说不，那我就不做了。看来我没法得到我想要的东西。”在这个行业里，你会学到一件事：你永远不可能拥有一套完整的数据集。如果你等着数据集齐全，那就等太久了，已经来不及了。我在这些会议上做的很多事情，就是决定我们要在某项决策上承担多大风险，或者是否要承担风险。You want progress to happen fast, so you kind of lay down the hammer. I would say the average engineer doesn’t understand the stakes or the urgency of how this is going to impact Intel’s bottom line, how it’s going to impact our customer. They just have no visibility into those issues. They will typically have a certain set of criteria that they want to go capture. They’ll hit boundaries of, “I asked for something and someone said no, and I’m done. I guess I can’t have this thing that I asked for.” One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you’ve waited too long. It’s already too late. A lot of what I end up doing in those meetings is deciding how much risk we’re going to take on a certain decision or not take on a certain decision.

你得说：“听着，我们现在要不要开始？要不要开始拿生产冒险？”因为你是在拿利润冒险，也是在拿收入冒险。我担心你会让我显得像个恶棍，因为我正在对大家严厉施压。这可真是个好名声啊。这确实传达了紧迫感。每一天都很重要。你能不能带我了解一个可能出现的具体问题？你今天早上看到的例子之一就是外延结节。“Epi”是“epitaxy”（外延）的简称，指在现有材料上生长新材料。芯片制造商让气体流过加热的晶圆，气体中的原子会留在晶圆表面。下方材料的晶体结构会起到模板的作用。每个新原子都会与下方的原子对齐，新的一层也就延续了相同的晶体结构。芯片制造商在芯片制造的多个阶段都会使用外延技术。You need to say, “Look, do we go now? Do we start risking production?” Because you’re risking the bottom line. You’re risking revenue. I’m worried you’re going to put me in the light of being an ogre because I’m putting the hammer down on people. That’s a great reputation to have. It’s really conveying urgency. Every day counts. Can you walk me through a particular issue that might come up? One of the examples you saw this morning is epi nodules. Epi is short for epitaxy, which means growing new material on top of an existing one. Chipmakers flow gases over a heated wafer, and the gases leave atoms on its surface. The crystal structure of the material underneath acts as a template. Each new atom lines up with the atoms below it, and the new layer continues the same crystal. Chipmakers use epitaxy at several stages of making a chip.

在 Kevin 描述的步骤中，他们利用它在栅极两侧生长出作为源极和漏极的小晶体。在外延层沉积过程中，我们会出现异常生长，长出一个像肿瘤一样的小东西。它长得特别快。这会造成问题，因为一个外延区可能会与错误的外延区短接，导致晶体管无法工作。接下来，你就得想办法逐步缩小问题范围，找出解决方案。过去十年来，英特尔的芯片一直具备一项名为 Processor Trace 的功能。开启后，它会开始记录程序运行的所有代码，并捕获足够详细的信息，让你之后能够重建每一次函数调用。大多数公司并不需要如此详细的信息。但 Jane Street 需要：他们必须调查交易系统中一些转瞬即逝的特定时刻——比如对网络数据包的响应延迟。In the step Kevin describes, they use it to grow the source and the drain as small crystals on either side of the gate. During the deposition of our epitaxy, we get abnormal growth, a little thing like a tumor. It’s growing super fast. That causes problems, because one epi will short to the wrong epi and you get transistors not working. Then you’ve got to narrow it down to how you’re going to fix it. For the past decade, Intel’s chips have had this feature called Processor Trace. When you turn it on, it starts recording all the code your program runs, and it captures enough detail that you can go back later and reconstruct every single function call. Most companies don’t need that level of detail. But Jane Street does: they need to investigate specific, fleeting moments in their trading systems—things like a delayed response to a network packet.

这些事件往往太过短暂，大多数调试工具都捕捉不到。因此，Jane Street 的一位工程师注意到 Processor Trace 后，便开始尝试使用它。随后，他和一位暑期实习生将这番探索转化为一款名为 magic-trace 的新工具。magic-trace 利用 Processor Trace 的输出，呈现出截至某个特定时刻之前每一次函数调用的历史记录。这个项目完全是自下而上发展起来的——起初，只是一位工程师觉得这件事很有价值。如今，Jane Street 的交易员和开发人员每天都在使用 magic-trace。如果你想加入一家信任你、让你去追求自己认为最重要的想法的公司，Jane Street 正在招聘研究人员和工程师。访问 janestreet.com/dwarkesh，了解更多信息。Those events tend to be too brief for most debugging tools to catch. So when one of Jane Street’s engineers noticed Processor Trace, he started playing around with it. And then he and a summer intern turned that exploration into a new tool called magic-trace. Magic-trace leverages the output from Processor Trace to give Jane Street a history of every function call leading up to a specific moment of interest. This project was completely bottom-up—it started just as something that one engineer thought would be valuable. And now, traders and developers across Jane Street use magic-trace every single day. If you want to work somewhere where you’re trusted to pursue the ideas that you think matter most, Jane Street is hiring researchers and engineers. Go to janestreet.com/dwarkesh to learn more.

你们今天早上看到的其中一项，是我们正在研究的一种特殊清洗工艺，它可以消除结节。结节会沉积下来，然后我们再把它清除掉。其他一些讨论则涉及结节的来源。要消除结节的源头。这里有个问题：你们如何判断它的来源是什么？大多数情况下，我们会高度并行地开展工作。你们如何判断？要解决问题，最简单的方法并不总是显而易见，所以我们会同时尝试所有可能的解决方案。有时候，最终奏效的并不是你最先想到的那个。一旦我们认定这是影响这项技术的一项主要问题，就会由这个“热门议题”会议介入。这就是我们如何协调工程团队的资源，从而加快工作的进度。你提到有一种快速通道流程，如果晶圆成为某项实验的瓶颈，就可以让它们更快地流转。One of the pieces that you observed this morning was a special clean that we were looking at, which would eliminate the nodule. The nodule would deposit, and then we’d get rid of it. Some of the other discussion was about the source of the nodule. Get rid of the source of the nodule. There’s some issue. How do you decide what the source of it is? For the most part, we work highly parallel. How do you decide? It’s not always evident what the easiest way to fix the problem is, so you work on all the potential fixes. Sometimes it’s not the one you expect first. Once we’ve identified it as a primary problem for the technology, that’s where this Hot Topics meeting gets involved. That’s how we align the resources into those engineering teams so that we can accelerate the work. You said that there’s some fast-track process where wafers can move through faster if they’re bottlenecking some experiment.

我们在工厂里有一套分级系统，称为 hot box。hot box 的每个等级都会让生产速度快上一些。这只是工厂对特定批次的优先级安排，也就是那批正在工厂里流转的硅片。我们最高等级的 hot box——HotBox 1——会飞速通过工厂。它在每一台设备上都享有优先权，但会拖累整个工厂的运转。如果你问工厂里的员工，他们不喜欢动用这张牌，因为为了让它跑得飞快，你就得低效地使用设备。你可以把它想象成一条高速公路，其中专门留出一条拼车车道，所有人都可以用，但你会说：“好，这条车道只供拼车使用。”这就是我们的 HotBox 1。其他车辆都让出这条车道，只有那一个实验可以飞驰而过。We have a tiered system of what we call hot boxes in the factory. Every grade of hot box goes a little bit faster. It’s just how the factory prioritizes that particular lot, that block of silicon that’s running through the factory. Our highest grade of hot box, HotBox 1, races through the factory. It gets priority at every single tool, but it’s a drag on the entire factory. If you had a factory person in here, they don’t like playing that card, because you end up using the tools inefficiently so that you can go super fast. Think of it as a highway, and you set aside that one lane for the carpool, which everyone could use, but you’re saying, “Okay, it’s just the carpool.” That’s our HotBox 1. Everyone clear out of that lane except for that one experiment, and that one experiment races down the highway.

用钌替代铜线Replacing copper wires with ruthenium

Kevin 的工作是决定现在什么可以进入生产线，但就在前一天，我和 Jack Kavalieros 一起去了英特尔的研究实验室，看看那些还没准备好用于当前工艺节点的构想。我们先从布线谈起。晶体管只有连接到其他晶体管后才有用，而在现代芯片上，这需要在晶体管上方堆叠十几层金属导线，这些导线被称为互连线。这些导线由铜制成，但随着尺寸缩小，铜开始面临难题。英特尔正在探索一种替代材料：钌。钌的电阻率更高，那你们为什么要探索将钌用于未来技术呢？有意思的是，随着铜线尺寸不断缩小，你会遇到一些挑战。比如，通常需要先沉积一层衬层，才能用铜填满这些线槽。Kevin’s job is deciding what goes onto the production line now, but the day before, I went to Intel’s research lab with Jack Kavalieros to see ideas that aren’t ready for the node yet. We started with wiring. A transistor is only useful once it’s connected to others, and on a modern chip that takes more than a dozen layers of metal wire stacked above the transistors, called interconnect. Those wires are made of copper, and as they shrink, copper starts to run into trouble. Intel is exploring a replacement: ruthenium. Ruthenium has higher resistivity, so why are you guys exploring ruthenium for the future? Interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. For example, copper typically requires a liner in order to deposit the copper to fill those lines.

钌在这方面很不一样，因为它是一种我们确实可以蚀刻的材料。因此，蚀刻钌之后，我们就不需要衬层了。现在把这些尺寸缩小到非常精细的程度，如果能用无衬层的结构取代这种电阻较大的衬层，钌就开始占优势了。到了某个临界点，钌的导电性会好得多，电阻率也会低于铜。这个临界点大约在 20 纳米的间距范围内。也就是说，你可以想象，间距的一半是金属线，另一半是将它们隔开的介电材料。那么衬层是什么？可以把它想成类似胶水层或过渡层的东西，我们需要它来沉积铜，使铜附着在上面，并与下方的铜线相连。这些铜线彼此交错并相互连接。Ruthenium is very different in that regard because it’s a material that we can actually etch. As such, by etching it, we don’t need that liner. Now you scale those very fine dimensions, and if you can trade off that resistive liner with no liner, ruthenium starts to win. There is a crossover point where ruthenium will have much better conductivity, better resistivity than copper. That’s roughly in the 20-nanometer pitch range, which means, if you can imagine, half of the pitch is your metal line, and the other half is the dielectric that isolates them. So what is the liner? Think of it almost like a glue layer or transition layer that we need in order to deposit the copper and have it stick, and have it make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other.

但每次沉积铜时，下面总是会有一层衬层。过去，这层衬层可能占整个导电路径相当大的比例。但随着时间推移，我们不断缩小尺寸、使它变得更薄，于是铜又重新成为有力的竞争者。我很好奇的一点是，你们如何判断一项技术已经成熟，可以用于大规模量产？在 10 纳米节点时，你提到你们从铜转向了钴，而这可能会带来一些问题。你们如何判断这项技术能够大规模应用？将这些材料集成到晶体管生态系统这样复杂的系统中，涉及许多不同的组成部分。可扩展性是一方面，能否实现集成则是另一方面。当时我们决定采用钴，是因为它是最有希望的方案。But every time you deposit copper, you’ve always had a liner underneath it. In the past, that liner may have been a significant portion of the entirety of that conduction path. But over time, we’ve scaled it, made it thinner, and so copper comes back into play as a contender. One thing I’d be curious to know is how you decide that a technology is mature and ready for high-volume manufacturing. With 10 nanometer, you were mentioning you guys moved on from copper to cobalt, and there were potential issues with that. How do you decide that this technology is going to work at scale? The integration of these materials into such a complex system as the transistor ecosystem involves many, many different components. The scalability is one part, but its ability to integrate is another. At the time we made a decision for cobalt, it was the forerunner.

为什么堆叠晶体管需要十年才能问世Why stacked transistors take a decade to ship

当时的结果更理想。但随着我们与外部生态系统合作，包括提供这些材料的供应商生态系统，以及我们将这些材料与之集成的工具，我们发现后续可能会出现一些解决方案，让铜重新成为两者中表现更好的选择。事情确实就是这样发展的。对于我们研究的每一项技术，都会评估多种方案。随着制造级产品的交付期限日益临近，我们必须做出决定。当时领先的方案是钴。现在又变成了铜，或许将来会是钌。 我很想听听你对 CFET 的看法，也就是把晶体管堆叠在一起。这方面进展如何？能不能不断增加层数？只能堆两层吗？能堆三层、四层吗？最多能堆多高？ 目前正在评估 CFET。不只是我们，我们的竞争对手也在评估，外部实验室也在研究它。它代表了可堆叠性的极致。过去我们不得不把晶体管压得越来越紧，而现在我们可以在某些方面放宽限制，因为我们要把晶体管堆叠起来。但堆叠并不意味着它们之间无需互连。正如我们在新闻稿中提到的，过去位于顶部、甚至底部的连接，现在必须从晶体管之间垂直穿过。这带来了新的挑战，因为开挖沟槽并填充沟槽时，随着纵横比不断增大，难度也会越来越高。The results were stronger at the time. But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, we find solutions down the road that may bring copper back in line as being the stronger of the two. That’s exactly what happens. Every technology that we go through, we will evaluate multiple options. As we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision. The leading option at the time was cobalt. Now it’s copper again, and perhaps in the future it’ll be ruthenium. I’d love to get your thoughts on CFET, basically stacking the transistors on top of each other. What is progress like there? Can you keep making more and more layers? Is it just two? Can you go three, four? How high can you get? That evaluation of CFET is currently underway. Not just by us, by our competition. Labs externally are looking at it. It is the ultimate in stackability. We’re taking transistors that had to be compressed more and more, and we’re relaxing that in some ways because we’re going to stack them on top of each other. But the act of stacking does not mean that they’re not interconnected. What used to be connections on the top or even on the bottom, as we’ve seen from our press release, now has to go vertically in between the transistors. That’s a new challenge because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult.

这并不像把晶体管堆叠起来那么简单，因为你还得考虑如何将它们互连。问题是不是在于要通过刻蚀形成那个深孔？刻蚀的深宽比是其中很重要的一部分。我们正在与供应商合作，推动这方面的发展并加以改进；但另一个问题是，如何填充那些极其微小的空间。因为填充时有时会留下气隙，或者留下始终无法完全填满的孔洞，这并不理想。我想，这个实验室里应该有一种能够运作的 CFET 版本。那么，目前能运作的是哪种晶圆或工艺？接下来是什么？再往后的步骤又是什么，直到它进入完整的大批量生产流程？在这些技术的发展过程中，尤其是对于 CFET 这样更复杂的架构而言——它不只是基础化学工艺或一种材料，而是一套完整的架构——我们必须制作短流程验证载具，以便更快地完成验证。It’s not as straightforward as stacking the transistors, because you still have to think about interconnecting them. Is the issue there the etch to get that deep hole? Aspect ratio for the etches is a big part of it. We’re working with our vendors to evolve on that and to improve that, but it’s also what you fill those very tiny spaces with. Because filling can sometimes leave air gaps or holes that are never really filled, and that’s not ideal. I assume there’s a version of CFET that works inside this lab. What is the kind of wafer or process that is working right now? Then what’s the next step? What’s the next step after that, until it’s inside the full high-volume process? Part of the process of evolving these technologies, especially something more complex like an architecture — not just a basic chemistry or a material, but a full architecture like CFET — is that we have to make short-loop vehicles that can give us faster turnaround.

正常的制造流程可能需要一个月甚至更长时间，才能完成其中数千个步骤。我们的目标是将这一流程拆分成各个单元，并对它们进行验证。我们利用短流程测试载体获取电学参数和化学参数，以解决其中的一些难题和障碍。解决这些问题后，再将它们组合起来，构成更复杂的测试载体。你会发现这里的东西都很简单：你可能是在制造二极管，也可能是在制造电容器，它们都是晶体管的组成部分。随着这些器件不断演进、性能逐渐增强，我们会将它们组合起来，进入下一阶段，可能就是晶体管本身。以 CFET 为例，你可能不会选择在四条纳米带上再叠加四条纳米带。The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them. We take advantage of short-loop vehicles that can give us electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps. Once we’ve resolved them, then we combine them into a more complex test vehicle. What you would find in here is something very simple. You might be making a diode, you might be making a capacitor, which are components of the transistor. As those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself. In the CFET example, you might not choose to do four ribbons on top of four ribbons.

你也可以选择先做一对一的结构，因为要处理高度大得多的结构，其纵横比自然会变得越来越难应对。这样我们就能得到一个简化版的 CFET，其中 NMOS 只有一根导线，PMOS 也只有一根导线。这能简化我们的工作，但仍有助于我们评估器件的堆叠方式以及它们如何互连。不过，这里的特征尺寸已经小到最终所需的程度了吗？还是说尺寸更大？哦，当然了。有些情况下，至少已经一样小了。比如，你可能听说过二维材料，也就是所谓的过渡金属二硫族化合物。这类材料非常非常薄，本质上就是由单原子层构成的材料。这些材料可以在这个实验室里进行沉积。我们可以评估这些薄膜的导电性、与其形成电接触的能力，以及调控其导电性的能力——而这正是晶体管的功能。You might just choose to do one on one, because naturally the aspect ratio of dealing with something that much taller becomes more and more challenging. So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS. That simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect. But are the feature sizes here as small as they will be eventually? Or are the feature sizes bigger? Oh, absolutely. In some cases, at least as small. For example, you’ve heard of 2D materials, these transition layer dichalcogenides, as they’re called. They’re very, very thin materials. They’re essentially one monolayer of atoms that we deal with. Those depositions can happen in this lab. We can evaluate those films in terms of conductivity, our ability to contact them, our ability to modulate that conductivity, which is what the transistor does.

所以，是的，我们不仅能够沉积尺寸极小、薄至原子级的薄膜，还能印制非常精细的特征。我们拥有 EUV 技术或电子束技术，可以印制非常精细的特征，与我们最终在生产中制造的特征类似。 我想说的是，由于缺乏对这一工艺的背景了解，我直觉上不太明白：如果现在已经能制造出尺寸如此之小、可用于工作的 CFET 特征，为什么还要等 10 年才能用到我的手机里？我理解这需要一个过程，但为什么这个过程会这么漫长？ 如果涉及的是 CFET 这样的架构，而不是一种新型材料，答案会略有不同。当然，材料面临着沉积、刻蚀和去除等方面的挑战。它们与上下其他层的兼容性，以及所有类似问题，都必须先经过研究，之后才能将其应用于生产线。So yes, we do have the ability to not only deposit films that are very small and thin to the atomic scale, but also print very small features. We have EUV technology, or E-beam technology, that can allow us to print very small features similar to what we will eventually make in production. I guess I don’t understand intuitively, lacking the context in this process, if you have the features that are as small for a working CFET right now. Why will it take 10 years for it to be in my phone? I understand that there’s a process, but why is it such a long process? The answer is slightly different when you’re dealing with an architecture like CFET versus a novel material. Materials have, of course, the challenges of being deposited, etched, removed. Their compatibility with other layers above and below, all those things have to be researched first before you put them in a production line.

一种架构看起来可能只是简单的演进。“哦，你们接下来要把纳米带晶体管并排放置。为什么不干脆把它们堆叠起来呢？”但当然，堆叠会增加蚀刻、沉积和清洗工艺的纵横比，而这项技术可能还没准备好。不过，如果你们已经做到这一步，那说明有一种成熟可用的技术版本了，对吧？没错。我们已经做出了一个简化版本，它未必比我们目前的纳米带并排技术更有优势，但我们还需要进一步改进，比如让它包含两条纳米带，或者加入合适类型的金属和介电材料，以便充分发挥这种器件的性能。明白了。所以这就像一个漫长的过程——有上千个不同的步骤，必须以非常独特的方式协同完成，才能让性能达到与前代技术相当的水平，甚至超越它。An architecture may seem like a simple evolution. “Oh, you’re making nanoribbon transistors next to each other. What’s wrong with just stacking them?” But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, and the technology may simply not be ready yet. But if you’ve already made it here, there’s a version of the technology that’s ready, right? Correct. We’ve made a simplified version that may not be an advantage over our current side-by-side technology of nanoribbons, but we need to evolve it to make it maybe two nanoribbons, or to add the right type of metals and dielectrics, in order to extract the maximum performance out of that device. Got it. So it’s like a long tail of— There’s a thousand different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.

这些想法通常会在哪些环节行不通？比如说，你有 20 种想法，涉及二维材料。你会如何判断某种材料确实不值得继续研究？有时，我们会发现材料的某些基本特性与我们其余的加工流程不兼容。最初阶段的实验可能只是非常简单的沉积。你会说：“好，我可以沉积薄膜、观察它、测量它。但一旦尝试在它上面制作接触，什么都粘不住。”问题可能简单到只是附着力不够。工艺的下一步根本无法附着在这种材料上。因此，你可能仅仅因为这样一个简单的问题就排除某种材料。更复杂的挑战可能是，后续加工过程中发生的气体相互作用会影响下游工艺步骤。Where do the ideas tend to fail? You have 20 ideas like 2D materials. What is the way in which you decide this is actually not worth pursuing further? Sometimes we discover fundamentals about the material that will be incompatible with the rest of the processing that we do. The first level of experiments may simply be very simple depositions. You say, “Okay, I can deposit the film, I can look at it, I can measure it. But the moment I try to make a contact to it, nothing sticks.” It could be something as fundamental as the adhesion. The next step in the process simply has no way to adhere to the material. So you may rule out a material because of something as simple as that. More complex challenges might be that the subsequent processing may have gaseous interactions with downstream steps.

例如，我已经沉积了薄膜，也用其他材料覆盖了它，但这些材料并不能形成气密封装。因此，在工艺流程中的第三、第四甚至第五步，仍可能与薄膜发生相互作用并改变其性质。这会使它变得不稳定，所以我们现在必须为这一工艺找到更可靠的气密封装方案。如果我们找不到控制它的方法，那这条路对我们来说就走不通了。For example, I’ve deposited the film, I’ve capped it with other materials, but they’re not hermetic. So my third or fourth or fifth step in the process may actually still interact with it and change its properties. That makes it unstable, and now we have to find better hermetic sealing for that process. If we don’t find a way to control it, then it’s a dead end for us.

混合键合与芯片间瓶颈Hybrid bonding and the chip-to-chip bottleneck

晶体管堆叠仍处于研究阶段。整颗芯片堆叠已经投入量产，它解决的是另一个问题：不同芯片之间如何通信。现代计算机由多个部分组成，每个部分都针对不同任务进行了优化。例如，英伟达的 Blackwell 数据中心 GPU 将两颗大型处理器芯片连接在一起，周围还配有八组高带宽内存堆叠。这些芯片必须不断相互传输数据。在人工智能领域，数据传输的速度往往才是限制工作负载完成速度的因素，而非原始计算能力。想象两颗芯片并排放置，通过彼此相对的边缘进行通信。如果把每颗芯片的宽度和长度都扩大一倍，电路面积会变成四倍，但用于连接的边缘长度却只会变成两倍。Stacking transistors is still in the research lab. Stacking whole chips is already in production, and it tackles a different problem: how separate chips communicate with each other. Modern computers are divided into multiple parts, each optimized for a different task. For example, Nvidia’s Blackwell data-center GPU joins two huge processor chips and surrounds them with eight stacks of high-bandwidth memory. These chips have to constantly send data back and forth with each other. And in AI, the speed of that traffic, not the raw computation itself, is often what limits how fast the workload finishes. Imagine two chips side by side, communicating through their facing edges. If you double each chip’s width and length, you’ll have four times the area for circuitry, but only twice the edge length for connections.

这就是面积与周长问题。随着晶体管变得越来越密集，芯片的计算能力增长得比其数据传输能力更快。多年来，业界一直知道这个问题，因此发明了多种技术来应对。电路完成后，还必须经过最后两道工序：键合和封装。芯片制造完成后，仍需连接到其他芯片以及计算机的其余部分。这一步称为封装，在过去几十年里发生了很大变化。大致来说，可以这样理解封装技术的演进：最初，芯片并排排列，连接它们的导线从一颗芯片的侧面引出，连到另一颗芯片上。为了提高通信密度，业界引入了一块供多颗芯片共同安装的硅片，称为中介层。This is the area-versus-perimeter problem. As transistors become denser, a chip’s ability to do computations increases faster than its ability to move data around. The industry has known about this problem for years, so multiple technologies have been invented to address it. The completed circuits must undergo two last operations: bonding and packaging. Once a chip is made, it still has to be connected to other chips and to the rest of the computer. That step is called packaging, and it has changed a lot in the last few decades. At a high level, you can think of the evolution of packaging like this: initially, chips were laid out side by side. Wires connecting them went out the side of one chip to another. To allow for more communication density, the industry introduced a shared piece of silicon, called an interposer, for multiple chips to sit on.

芯片可以通过直接穿过中介层的布线与其他芯片通信。这种封装方式通常称为“2.5D”。提高连接密度的另一种方法是将芯片直接键合在一起。这样可以缩短芯片之间的连接距离，但这种方法的早期版本采用了焊料凸点，不仅体积较大，还会增加电阻。更好的做法是省去焊料，直接将两块芯片的信号线连接熔合在一起。这称为混合键合，也是半导体行业投入最多的技术之一。混合键合的做法是先将一块芯片的铜互连与另一块芯片的铜互连对准，然后将两块芯片压合并加热，使互连结构膨胀并跨越芯片之间的间隙。A chip can talk to other chips through the wiring that runs directly through the interposer. This type of packaging is often called “2.5D”. Another way to increase connection density is to bond chips directly to one another. This allows for shorter connections between chips, but the early versions of this idea used solder bumps, which are bulky and increased resistance. It would be better to skip the solder and fuse the signal wire connections of the two chips directly to each other. This is called hybrid bonding, and it is one of the technologies the semiconductor industry is investing in the most. Hybrid bonding works by aligning the copper interconnects of one chip with those of another. Then these chips are pushed together and heated so their interconnects expand and bridge the gap between the chips.

这一工艺还会在铜键合处周围形成绝缘表面。因此，去除焊料凸点后，连接就能变得密集得多。但这项技术直到现在才进入大规模量产，是因为要花一段时间才能解决它带来的对准和缺陷难题。在封装实验室里，我问了英特尔先进封装技术开发团队的总监泰勒·奥斯本，他们是如何将这项技术付诸实践的。英特尔花了50多年时间优化CPU的速度。但其中许多优化——例如缓存、分支预测和推测执行——都会降低可预测性。完全相同的指令，有时需要4个周期才能执行完，有时却要300个周期。当数十亿条指令堆叠在一起，并通过多个线程和核心执行时，这些非确定性因素会不断累积，导致各种难以复现的错误。This process makes the insulating surfaces around the copper bond as well. And so by removing the solder bumps, you end up with much denser connections. But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced. In the packaging lab, I asked Tyler Osborn, a director in Intel’s advanced packaging technology development group, how they put this into practice. Intel has spent over 50 years optimizing its CPUs for speed. But lots of these optimizations—like caching and branch prediction and speculative execution—reduce predictability. The exact same instructions can take four cycles to execute one time and 300 the next. When you stack billions of instructions together and execute them across multiple threads and cores, these non-determinisms compound into all sorts of hard-to-reproduce bugs.

如果你做的是严肃的系统开发，那肯定遇到过这种情况。Antithesis 通过一个有点疯狂的办法解决了这个问题：他们造出了一台 100% 确定性的计算机。他们找出了 Intel x86 架构中所有可能泄漏非确定性的入口——网络数据包、磁盘读取、温度传感器，甚至时间本身。然后，他们要么把这些入口全都封死，要么接入受控模拟。这台确定性计算机只是一个基础。在它之上，Antithesis 构建了一个测试平台，能把数年生产环境加固的工作压缩到几分钟内完成。它会让你的软件在数千个并行世界中运行，注入故障，并智能地引导每个世界，逐步逼近那种十亿分之一概率的故障——你自己根本无法测试出来的故障。我在前几期提到过的 Antithesis 其他那些不可思议的功能，背后靠的都是这种确定性。If you work on serious systems, you’ve definitely experienced this. Antithesis solved this by doing something a bit crazy: they built a 100% deterministic computer. They identified every single door in Intel’s x86 architecture where non-determinism could leak in—network packets, disk reads, temperature sensors, even time itself. And they either welded each of these shut or slotted in a controlled simulation. This deterministic computer is just a foundation. On top of it, Antithesis built a testing platform that compresses years of production hardening into minutes. It runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one-in-a-billion failure that you’d never be able to test yourself. This determinism is what’s behind all the other insane Antithesis features that I’ve mentioned over the past few episodes.

它能让你复现任何 bug，并回溯测试运行中的任意时刻。最重要的是，它能让你——或者你的智能体——追查每一次故障的根本原因。访问 antithesis.com/dwarkesh 了解更多。 混合键合有两种不同的方式：芯粒对芯粒，以及芯粒对晶圆。你或许可以谈谈这两种方式各自的优势，以及实际应用中哪一种效果更好。 当然。在英特尔内部，你说的芯粒对芯粒，我们通常称为晶圆对晶圆。我们会取一整片晶圆，再取另一片晶圆，把它们键合在一起。这种方法目前在 CMOS 图像传感器行业非常流行，事实上，它几乎已成为该行业的主流。人们也在研究将它用于其他领域，比如存储器堆叠。也有人发表了各种各样的相关构想。It’s what lets you reproduce any bug and time travel to any point in the test run. Most importantly, it’s what lets you—or your agents—trace every failure back to its root cause. Go to antithesis.com/dwarkesh to learn more. Two different ways you could do hybrid bonding: die to die and die to wafer. Maybe you can talk about the advantages of both and which one actually practically works better. Sure. Around Intel, what I think you’re referring to as die to die, we typically call wafer to wafer. We actually take a full wafer and another wafer and bond them together. That’s an approach that’s really popular right now in the CMOS image sensor industry. In fact, it basically dominates it. It’s being looked at for other things like memory stacking. People have published ideas about all kinds of stuff.

不过，这样做的一项挑战是，你需要彼此完美匹配的裸片，而且要有完全对应的左手版和右手版，因此必须能够精准地将一片键合到另一片上。裸片尺寸必须一一对应，这本身就是个难题。如果上下两片不是完全相同的器件设计，就会出问题。采用晶圆对晶圆键合时，难点在于确保两片晶圆的分选结果高度匹配。也就是说，这里的良品阵列要与那里的良品阵列相匹配。如果两者完全一致——良品和不良品的位置都一一对应——那么这道工序中良品裸片的良率就能达到 100%。但这种情况的可能性非常低。两片晶圆的分布会有一定的随机性，而这种随机性会导致良品与不良品键合，造成损失。相比之下，采用芯片对晶圆键合时，我可以自行决定配对方式。One of the challenges with that, though, is that you need dies that perfectly match each other, and are perfectly left-handed and right-handed, so you have to be able to bond exactly one to the other. One-to-one die size is a challenge. If they’re not the exact same design device on top and bottom, that’s a problem. With wafer to wafer, it’s challenging to make sure that you have wafers that match really well in terms of the sort. So sort good array here versus sort good array here. If they match exactly — good die and bad die all match — I can get 100% yield of that operation of the good dies. But the chances of that are very low. There’s going to be some randomization of the two, and whatever that randomization is, will be loss of good bonding to bad. Whereas with chip to wafer, I can dictate the terms.

我可以将晶粒切割分离，获得经过芯片级测试的已知良品裸片，然后只把已知良品键合到已知良品基底上。那么你认为，未来你们会采用芯片对晶圆的方式进行混合键合吗？我认为两种方式都会采用。我们肯定具备两种方式的能力。这主要取决于客户需求和架构设计，但在逻辑芯片对逻辑芯片的领域，芯片对晶圆的方式确实很有意义。你刚才提到，从先进封装发展到混合键合，焊盘间距在不断缩小。还能进一步缩小多少？这是个很好的问题。正如我们刚才所说，15年前，一级互连的间距是130至150微米。如今在高量产中，我们在Foveros上实现了25微米的间距。这里我们已经做到10微米以下了，不过此前已经有相关文献发表。I can singulate and have known good dies that I’ve tested at the chip level, and then only bond known good to a known good base position. Do you think then chip to wafer is the way that you’ll do hybrid bonding in the future? I think we’re going to do both. We definitely have the capability to do both. It’s really customer and architecture driven, but certainly chip to wafer in the logic-to-logic space makes a lot of sense. You were explaining that going from advanced packaging to hybrid bonding, the size of the pitches is decreasing. How much further could that go? That’s a wonderful question. Historically, like we were saying, 15 years ago first-level interconnect was 130-150 micrometer pitch. Today in HVM, we’re doing 25 micrometer pitch in Foveros. Here we’re doing sub-10, but there’s already been literature out there.

事实上，封装领域每年规模最大的会议是 5 月举行的 IEEE ECTC 会议。今年会上有一篇论文展示了间距为 0.45 微米的混合键合器件的可靠性数据。你可以想象，这相比我们目前在高量产阶段的水平，密度又提升了整整一个数量级。这种可扩展性已经得到验证，所以我认为这方面还有很长的发展空间。在互连方面，单片晶圆内部的互连通常相隔多远？在晶圆厂的后端工艺中，你可以想象，封装下方的几层通常尺寸在 1 微米到 0.5 微米左右。因此，如果能将封装的尺寸推至 0.5 微米或更小，就几乎可以考虑移除芯片顶部的若干层，并将硅内部较低的一层与另一层连接起来。In fact, the biggest conference every year in packaging is the IEEE ECTC conference that happens in May. There was a paper there this year showing reliability data on a 0.45 micron pitch hybrid bonded device. So you can imagine that’s a whole other order of magnitude in density again from where we are right now in HVM. That scalability has already been proven. So I see a long runway there. Within interconnect, within a single wafer, how far separated are they usually? In the back end of the fab, you can imagine the few layers below packaging are typically around one micron to a half micron in size. So if you can push packaging down to 0.5 microns or below, you can almost think about taking layers off the top of the die and connecting a lower layer within the silicon to another lower layer within the silicon.

混合键合的魅力真正就在这里。可以设想一下，未来甚至能减少两侧的互连层数，再把它们键合在一起，从而降低两个晶体管层之间的总 IR 压降。想到这项技术在这些领域能发展到什么程度，真的很令人兴奋。其实我很好奇……对于 AI 来说，混合键合如此强大的原因很容易理解，因为它能让内存带宽更高。但你刚才提到，散热等方面也存在一些问题。对于非 AI 应用，混合键合有什么优势呢？问得好。确实有一些公司正在研究将它用于非 AI 应用，甚至是客户端设备。我认为它在那里能发挥作用的一大优势，首先显然是同样的原始互连密度，尤其是在 CPU 和 GPU 这类组件之间。That’s really where the beauty of hybrid bonding happens. You could think someday about even having reduced interconnect layers on both sides that we can bond together and have less total IR drop between the two transistor layers. It’s really cool to think about where that could go once we get into those regimes. Actually, I am very curious about… For AI, it makes sense why hybrid bonding is so powerful, because then you can get higher bandwidth to the memory. But you were saying there are issues with heat and everything. What is the advantage for non-AI applications of hybrid bonding? Excellent question. There are companies out there that are looking at it for non-AI applications, even in client devices. One of the big things I think it can help with there is, number one, obviously the same raw interconnect density, especially between something like a CPU and a GPU.

但另一个方面是功耗。就像我们之前谈到的，互连越精细，接口的总功耗（以每比特的皮焦耳数计）就越低。在这些应用中采用混合键合，可以看作封装帮助降低整个系统功耗预算的另一种方式。这能带来诸多好处：在实际电气性能不变的情况下，功耗更低、发热更少。到目前为止，我们谈的都是如何制造更好的芯片。But the other one is around power. Like we talked about before, as you get to finer and finer interconnects, you can reduce the total power consumption, in picojoules per bit, for that interface. With hybrid bonding in those applications, you could think about that as another way that packaging can help reduce the total system power budget. That gives you lots of benefits: lower power, less heat, for the same benefit in terms of actual electrical performance. So far, this has been about making better chips.

没有足够的设备将芯片产量提高到十倍。There aren't enough tools to 10x chip production

这个问题的另一半是，如果 AI 实验室愿意为更多芯片买单，整个行业能生产多少芯片。我有机会和英特尔首席技术官 Pushkar Ranade 交流。我很想了解，全行业都依赖相同的供应商这一事实，究竟会如何制约你们提升产量。以这种 EUV 光刻机为例，ASML 每年生产不到 100 台。即便到了本十年末，他们也不打算把年产量提高到 100 台以上，或者大幅增加产量。这些设备必须由你们、台积电以及所有正在扩大产能的存储器制造商共同分配，比如 SK 海力士。这会如何限制你们满足所有这些需求、扩大生产规模的能力？这确实是一个限制因素。我们必须充分利用已经安装的产能。The other half of the question is how many chips the industry can make if AI labs are willing to pay for far more of them. I’m getting a chance to talk to Pushkar Ranade, who is the CTO of Intel. I’m very interested in understanding how the fact that the entire industry has to rely on the same suppliers bottlenecks your ability to ramp up production. For this EUV tool, ASML produces fewer than 100 of them a year. They don’t plan to produce more than 100 a year, or significantly more, even by the end of the decade. That has to be split between you, between TSMC, between all the memory makers who are ramping up production, like SK Hynix. How does that limit your ability to scale up to all this demand? It is a limiter. We have to make the most of the capacity that we already have installed.

我们会努力提高现有设备群的产出。不过，EUV 或 ASML 并不是唯一的瓶颈。它的瓶颈作用确实比某些其他设备更突出，但在很大程度上，我们看到所有设备都面临严重的供应短缺。尽管其他设备有多个供应商，但一旦你锁定了一套工艺流程——比如现在已经成熟的 18A——我们就需要特定的设备。我们不能随便找另一台设备来用于同一工艺。因此，我们只能依赖那一台设备和那一家供应商。这对 14A 的规划有什么启示？到了 2028 年，局面会变得异常复杂。你要如何规划，才能在产能爬坡时保有灵活性？可行的做法是——我们一直在这么做，而且通常大家也都这么做——尽可能确保从一个制程节点过渡到下一个节点时，设备具备最大的通用性。We’ll try to increase the output from our existing fleet of tools. But EUV or ASML is not the only bottleneck. It is definitely a bigger bottleneck than some of the other tools, but to a large extent, we’re seeing all equipment seeing tremendous supply shortage. Even though there are multiple providers of other tools, once you lock into a process flow — let’s say 18A, which is a mature process now — we need a specific tool. We can’t just go and get a different tool for the same process. So we’re locked into that one tool, one supplier, and we rely on that. What lessons does this give for 14A in terms of how you structure it? By 2028, it’s going to be such a crazy world. How do you structure things in such a way that you have flexibility in ramping? The way to do it — and we’ve been doing it, and generally everybody does it — is you try to maintain as much fungibility as possible going from one node to the next node.

从 18A 转到 14A，也许你会说，工具设备中有 80% 可以重复使用。当然，14A 的几何结构更密集，因此需要一些新的能力，也需要一些专用工具。你们是否清楚，制约你们每月最多能生产多少片晶圆的最终瓶颈是什么？即使你们决定投入无限资金进行资本支出，也会受到什么限制？考虑到现有约束，假设我们必须在给定的工具设备占地内尽可能提高产出，那么我认为提升是渐进式的，因为目前的工艺良率已经相当高了。如果良率已经很高，要再提高 1 个百分点就会非常困难，因为工艺已经经过精细调校。全球是否有足够多的工具设备，能让你们将先进制程的晶圆产量提高到现在的 10 倍？Going from 18A to 14A, maybe you would say 80% of the tool set can be reused. Then, of course, 14A would require some new capabilities because it’s a denser geometry, so it would require some unique tools. Do you have a sense of what the ultimate bottleneck is on how many wafers you guys could produce a month, even if you were to decide to invest infinity money into doing CapEx? Given the existing constraints, let’s say we had to maximize the output from a given footprint of tools, then I think it’s incremental, because the process today is already yielding pretty high. If your yield is already pretty high, getting every 1% extra yield is extremely hard because it’s already a finely tuned process. Are there enough tools in the world so you could 10X the amount of wafers you’re producing at the leading edge?

不是 10 倍，但大概是 2 倍，没错。这很有意思，因为过去十年，AI 行业的算力每年都增长 3 倍。你的意思是，这种增长根本无法持续下去。除非整个供应链——从设备供应商，到他们的供应商，再到更上游的供应商——所有人都扩大产能，否则产出就无法增加。 为了让听众对 AI 需求有多庞大，以及你们生产的产品能带来多少收入有个概念：你可以算一算，数据似乎表明，英特尔只要投入几十亿美元的资本开支，就能生产出足够多的芯片——或者说，足以支撑生产足够多芯片的逻辑芯片——从而让 AI 模型公司获得比如说 1000 亿美元的营收。当然，这条产业链上还有很多其他参与者，也包括存储器和其他东西。Not 10X, but probably 2X, yes. That’s quite interesting, because the AI industry for a decade has been 3Xing compute year over year. You’re saying that just can’t continue. Unless the entire supply chain — starting from the equipment suppliers, their suppliers, their sub-suppliers — unless everybody produces more, you can’t increase the output. Just to give the audience a sense of how big the AI demand is and how well it monetizes the products you guys are producing: you can crunch the numbers, and the numbers seem to suggest that just a couple billion dollars of CapEx on Intel’s account results in enough chips — or the logic for enough chips — to produce, say, $100 billion of revenue for the AI model companies. Of course, there are so many other players within that stack. There’s also memory and other things.

但令人难以置信的是，几十亿美元的资本支出可以分摊到许多年里，却能每年带来 1000 亿美元的收入。这似乎意味着，到了某个时候，这种收益应该会逐渐向下传导。也许有一天，AI 实验室会直接说：“我们把所有东西都买下来。你们能生产多少就生产多少。未来的收入流我们来兜底。”已经有一些早期迹象表明，这种情况可能真的正在发生。需求信号实在太强了。不过，我想你刚才是在说，价值正不断汇聚到技术栈的顶端。实际上，我们的产业从 30 到 40 年前、甚至更早的完全垂直整合模式，转变成了一个高度水平分工的产业：有晶圆代工厂、设备制造商，还有它们的供应商。如今，每家超大规模云服务商都在设计自己的芯片，而且它们的规模极其庞大。But it’s crazy that a couple billion dollars of CapEx, which can be amortized over many different years, produces $100 billion of revenue every single year. That seems to suggest that at some point that should percolate down. At some point, the AI labs could just say, “We’ll just buy everything. Produce as much as you can. We’ll guarantee future income streams.” There are early signs that could actually be happening already. The demand signals are just so high. But I think you were alluding to how the value is accumulating at the top of the technology stack. What is essentially happening is we moved from a fully vertically integrated industry 30-40 years ago, maybe longer, to a very horizontal industry, where you have foundries, you have equipment makers, you have their suppliers. Today, every hyperscaler is designing their own chips, and the scale of the hyperscalers is so large.

英特尔能赶上台积电吗？Can Intel catch up to TSMC?

一些模型公司，比如说，它们的需求非常旺盛，光靠自己就能轻松消耗掉一整座晶圆厂、甚至多座晶圆厂的硅片产能，而且它们显然有足够的资金来支撑这种需求。所以从某种意义上说，我们又在从一个横向分工的世界转向一个伪纵向整合的世界。它并非完全一体化的纵向整合，但可以说是虚拟的纵向整合。这项业务的规模经济究竟是什么样的？如果看看台积电和英特尔在先进制程上出货的晶圆数量，台积电超过英特尔三倍。规模经济在这个阶段能带来哪些优势？还是说，达到某个规模后，规模经济的效应就会减弱？这是个非常重要的问题。整个行业都依赖规模经济。如果看看所有先进制造企业，在半导体代工领域，规模经济效应可能最为显著。原因在于固定成本高得惊人。一座晶圆厂建成后，成本结构中大约有 80% 是固定成本。这意味着，每提高一个百分点的产能利用率，带来的收入增幅都会大得多。因此，这一点至关重要。我们会竭力争取晶圆厂产能利用率每提高一个百分点，也会争取晶圆厂产出每增加一个百分点。Some of the model companies, for example, their demand is so high they could easily consume an entire fab’s worth of silicon on their own, or multiple fabs’ worth, and they definitely have the capital to fund that. So in some sense, we are moving from a horizontal world again to a pseudo-vertical world. It’s not monolithically vertically integrated, but it’s kind of virtually vertically integrated. What is the nature of economies of scale in this business? If you look at how many wafers at the leading edge TSMC versus Intel is shipping, it’s upwards of 3X for TSMC. What kinds of advantages do you get at this point from economies of scale? Or is it that once you reach a certain point, the economies of scale get weaker? That’s a very important question. This entire business just relies on economies of scale. If you look at all the advanced manufacturing companies out there, in semiconductor foundries the scale economics is probably the purest. The reason for that is the fixed cost is just so incredibly high. Once you build a fab, like 80% of your cost structure is fixed. What that means is every extra percentage of utilization is adding far more in revenue. So it’s extremely important. We’ll fight for every extra percent of fab utilization, but also every extra percentage of fab output.

假设我今天在制造一些晶圆，良率是 60%。如果我改进工艺，让芯片良率提高到 65% 或 70%，带来的优势并不是线性的。相同的占地面积下，我能获得多得多的产出。因此，规模经济总是还有提升空间。这也是这个行业出现如此多整合的原因之一。正是因为这个原因，在先进制程节点上，如今只剩下三家晶圆代工厂了。在此过程中，许多公司干脆停止了制造业务。不知道你有没有看过……有一张图表显示，40 年前大约有 20 家晶圆代工厂。随着时间推移，晶圆代工厂的数量不断减少，直到今天只剩下三家。那么，追赶台积电的具体总体计划是什么？尽管台积电领先，但其最先进制程的需求远超产能；如今，N3 上的大多数产能都用于 AI 加速器，而且其中或许大部分都被英伟达一家占去了。Let’s say I’m making some wafers today and the yield is 60%. If I improve the process and the die yield becomes 65% or 70%, it’s not a linear advantage. I’m getting way more output for the given footprint. So there’s always room to improve the economies of scale. That’s one of the reasons why you’re seeing so much consolidation in this business. There are only three foundries left at the advanced node for that exact reason. Along the way, many companies just stopped manufacturing. I don’t know if you’ve seen… There’s a chart where 40 years ago there were like 20 foundries. Over time the number of foundries kept diminishing until today there are only three. What is then the concrete master plan to catch up to TSMC? Even though TSMC is ahead, there’s so much overflow demand at their leading edge, where N3 is now majority AI accelerators and maybe majority Nvidia alone.

现在对 CPU 和其他产品都有大量需求，而顺带一提，这些产品也是 AI 所需要的。AI 带来了巨大的 CPU 需求增长。你怎么看眼下这个机会？英特尔落后几年，而台积电的产能又远远供不应求。追赶台积电涉及多个方面。我们需要在规模上追赶。就像你说的，他们如今的晶圆制造规模比我们大得多，甚至也比三星大得多。规模上的追赶将是一个渐进的过程。如果你指的是单纯在技术上追赶，我认为我们已经做到了。我们的性能、功耗或面积密度可能还差几个百分点。但这种比较——哪家晶圆代工厂领先、哪家落后——只有在你整整落后一代、两代，或者领先一代、两代时才有意义。There’s all this demand for CPUs, for other things, which are also, by the way, needed for AI. There’s this humongous influx in demand for CPUs because of AI. How do you see this opportunity right now, where Intel’s a few years behind, while TSMC is just way oversaturated? Catching up to TSMC has multiple facets. The catch-up that we need to do is in scale. Like you said, they’re just a much larger wafer manufacturer today than we are, and even bigger than what Samsung is. Catching up in scale will be a gradual process. If you meant catching up in terms of just the technology, I think we’re already there. We might be a few percent off on performance or power or area density. But this sort of benchmarking, where one foundry is ahead or one foundry is behind, makes sense when you’re a whole generation behind or two generations behind or ahead.

只有当它对芯片产出、芯片面积，或功耗这类功能指标产生显著影响时，差异才有意义。但如果差距只有几个百分点，那就只是斤斤计较了，因为这并不是单一维度的问题。它不只是密度，也不只是原始性能。不同应用需要考量不同的指标。你可以有几个百分点的差距，但必须按时交付。你的执行力必须足够强，才能实现很高的良率，以支撑大规模、快速爬坡。实际上，这比在性能或面积上追赶几个百分点更重要。我看过一些 SemiAnalysis 的数据，似乎表明在晶体管密度方面，将于 2028 年推出的 14A 会与 N2 相当。首先，我对你们的基准测试结果有异议。That’s when it makes a meaningful difference in your die output or your die area or functionality like power. But if you’re within a few percent, you’re splitting hairs at that point in time, because it’s not very unidimensional. It’s not just about density, it’s not just about raw performance. Different applications require different vectors. You can be off by a few percent, but you need to be on time. Your execution needs to be such that your yields are very high to support very large and very rapid ramps. That actually is more important than catching up on a few percent in performance or area. I was looking at some SemiAnalysis numbers that seem to suggest that in terms of transistor density, 14A — which will come out in 2028 — would be comparable to N2. First of all, I would dispute your benchmarking.

但正如我所说，重要的是总体上要处于合理范围，而且表现非常可预测。此外，这也不是单一维度的问题。我们不会只造一种晶体管，比如说 14A 或 18A。我们会造几种不同类型的晶体管：有低漏电晶体管，也有高性能、高驱动电流晶体管。我们还会制造 SRAM，既有高密度 SRAM，也有高性能 SRAM。此外还有许多其他功能，比如模拟电路和射频电路。所有这些加在一起，才决定了一项技术是否具有竞争力。我想，这也让你们现在的资本支出变得更加重要。台积电今年的资本支出预计约为 500 亿美元，而你们预计约为 200 亿美元。如果你们现在采购的设备将决定谁能满足即将到来的这波惊人的 AI 需求，那么当前的资本支出差距就显得更加重要了，尤其是对比美国和其他国家时。But like I said, it’s important to be generally in the right ballpark and be very predictable. Also, it’s not unidimensional. We don’t build one type of transistor, let’s say 14A or 18A. You build a few different types of transistors. There’s a low-leakage transistor, there’s a high-performance, high drive current transistor. You’re building SRAMs. There’s a high-density SRAM, there’s a high-performance SRAM. There are many other functionalities like analog circuits, RF circuits. It’s the sum of all of those that makes a technology competitive. I guess that makes the CapEx you do right now even more important. TSMC is on track to do around $50 billion in CapEx this year. You’re on track to do around $20 billion. If the tools you’re buying right now will determine who can service all this crazy AI demand that’s coming up, it makes the difference in CapEx right now even more important, or for the US versus other countries.

是的，非常明显。如今拿我们和台积电比较有点不公平，因为他们基本上是为所有人提供晶圆代工服务，而我们主要是为英特尔提供代工服务。我们也会为其他客户提供代工服务。随着时间推移，我们的资本支出也会增加。英特尔在 20 世纪 60 年代末最初是一家 DRAM 企业。你们当时也生产 DRAM，后来把这项业务卖掉了。几年前，你们又出售了闪存业务。你对此怎么看？给观众补充一些背景：如今这些产业的规模都已达到数万亿美元，因为 AI 需求推动它们急剧扩张。显然，事后看来，出售闪存业务的时机可能不太明智。当时我们这么做自有充分理由。显然，没人能预见到如此庞大的需求。但如今，全球对算力的需求有多少就能消化多少，对存储器的需求也有多少就能消化多少。Yes, very much. It’s a little bit of an unfair comparison between us and TSMC today, just because today they’re a foundry for basically everybody and we’re largely a foundry for Intel. We’ll become a foundry for others. In due course, our CapEx will also grow. Intel started as a DRAM business in the late ’60s. You guys were producing DRAM, which you sold off. A couple years ago, you sold off your flash business. Thoughts on that? For context for the audience, these are now multi-trillion-dollar industries because they’ve just exploded as a result of AI demand. Clearly, in hindsight, probably not the smartest time to sell off a flash memory business. There were good reasons why we did that when we did. Clearly, nobody could see this enormous demand. But today, the world will eat up as much compute as can possibly be made, and it’ll eat up as much memory as can possibly be made.

我认为，如今内存的供应短缺比算力更严重。能不能让我概括一下我从你的预测中得出的结论？你可以告诉我说得对不对。新增产能实际上可以增长得非常快——大约只需 12 个月——但到本世纪末，产能增幅会非常有限。明年的产量可能高于人们的预测，但 2030 年的产量不会比人们的预测高出多少，除非整个供应链都迅速提升产能。现在已经是 2026 年年中，距离本世纪末没几年了。考虑到交付周期……假设你今天下了一笔巨额订单采购设备，而这些设备要 18 个月才能到货。I would argue that the supply crunch is larger for memory today than it is for compute. Can I summarize what seems to me the takeaways from your projections? You can tell me if that’s correct. That marginal production can increase actually very fast — on the scale of 12 months — but the amount of increase up till the end of the decade is extremely limited. Production could be higher next year than what people are forecasting, but production in 2030 is not going to be significantly higher than what people are forecasting. Unless the entire supply chain ramps up production very quickly. We’re already in the middle of ’26, so there’s not that many years until the end of the decade. Given the lead times… Let’s say you place an enormous order for tools today, and you’re looking at 18 months to get those tools.

到那时，基本上已经是2028年了。从那之后，如果你得新建厂房主体、建一座新晶圆厂，那基本上就要到这个十年末了。You’re already into basically ’28. From that point on, if you have to build a new shell, build a new fab, you’re basically looking at the end of the decade.

Terafab，以及从头重新思考晶圆厂格局Terafab, and rethinking the fab from scratch

我觉得聊聊你们和埃隆在 Terafab 上的合作会很有意思。那边现在是什么情况？嗯，埃隆公开谈过他想建一座晶圆厂。要么我们建 Terafab，要么就没有芯片。而我们需要芯片，所以我们会建 Terafab。想法大致也是一样的。他看到硅片、算力和存储器的需求都在大幅增长。我想他得出的结论是，自己的业务将需要大量硅片。他觉得也许应该全都自己来做。但这和造一辆车不同，这是一个极其精细、复杂的过程，因此我们认为可以合作，帮助他加快晶圆厂的建设。不过，由于设备环节存在瓶颈，全球硅片的净供应量似乎不会增加。I think it’ll be interesting to discuss the partnership you guys have with Elon on Terafab. What’s going on there? Well, Elon’s publicly talked about his desire to build a fab. We either build the Terafab or we don’t have the chips. And we need the chips, so we’re going to build the Terafab. Sort of the same thinking. He’s seeing just an enormous increase in demand for silicon, for compute and for memory. I think he came to the conclusion that his own businesses are going to require a lot of silicon. He thought maybe he should just do it all on his own. But unlike building a car, for example, this is such an intricate and complicated process that we thought we could work together to help accelerate his bringing up his fab. But because of the bottleneck at the tool level, it seems like the net amount of silicon in the world won’t increase.

只是说，也许如果有人要新建一座晶圆厂，就能获得有保障的供应；而如果他们使用别人的代工厂，就无法做到这一点。需要的不只是设备。晶圆厂确实需要大量电力、水和耗材，也有许多其他投入要素。不过，这些要素可以扩充，设备却做不到这一点。有些比其他要素更容易扩充，但确实如此。从某种意义上说，我们确实需要多得多的设备。但没错，我们也需要大得多的晶圆厂空间，也就是更多的洁净室产能。假如你把英特尔这样的代工厂考虑在内——它必须建造这些昂贵的设施，购买昂贵的设备——你觉得这种模式从根本上来看，经济效益会是什么样？它能否变得更经济，能否更快扩张？It’s just that maybe if somebody were to start a new fab, they would get access to guaranteed supply in a way that they wouldn’t have if they’re working with another person’s foundry. It’s not just tools. A fab does require a lot of power, a lot of water, a lot of consumables. There are many other input variables as well. But those can be scaled in the way that tools cannot. Some more than others, but yes. In one sense, yes, we need a lot more equipment. But it is true, we also just need a lot more raw fab space, raw clean room capacity. If you think of a foundry like Intel, which has to build these expensive facilities and buy expensive tools, I wonder what you think the economics of that fundamentally could look like, whether it could get more economical, whether it could scale faster.

就像我之前描述的，这是一个资本密集度极高的行业。如果你把过去 20 年、30 年、40 年建一座晶圆厂的成本画成图，我认为每 4 到 5 年就会翻一番。即使在晶圆厂内部，如果你看光刻的成本——这是最昂贵的环节，也就是图形化——它本身的成本增长速度还要更快。如今，一台高数值孔径（High-NA）EUV 扫描机及其所有配套设备的成本约为 4 亿美元。那么这意味着什么？如果这种增长速度持续下去，只是把这条线延伸下去，那么四年后图形化的成本会达到 8 亿美元左右吗？这似乎不太合理。一个很有意思的思考练习是问：有没有什么我们今天就能做、但也许 20 年前还做不到的事情，能够带来非常根本性的改变？Like I described earlier, this is an extremely capital-heavy business. If you just plot how much it costs to build a fab over the last 20, 30, 40 years, I think it’s doubling every 4-5 years. Even inside the fab, if you look at the cost to do lithography, which is the most expensive module — just patterning — that itself is doubling at more than that rate. Today, a High-NA EUV scanner and all its associated equipment costs like $400 million. So what does that mean? If that rate were to continue, if you just draw the line, does that mean four years from now the cost of patterning is going to be like $800 million? It doesn’t really make sense. A very interesting thought exercise is to ask, are there things that could be just very radically different that we could do today that we perhaps couldn’t do 20 years ago?

这是一个极其厌恶风险的行业，而且这种谨慎完全有充分的理由。你投入数百亿美元，当然不想冒任何风险。你希望继续沿用几十年来一直采用的做法。这不仅适用于半导体行业，基本上各行各业都是如此。如果你年复一年、几十年如一日地这么做，就会逐渐被这种观念彻底灌输。有些可能在英特尔工作的新工程师入职后，会被教导：“晶圆厂就是这么运作的，工艺流程就是这样。”他们便把这些当成了金科玉律，认为事情本来就该这么做。但如今制造芯片，这真的是最佳方式吗？这是个非常值得探讨的问题。我很想知道你暗示的是什么，因为可能性太多了：从想办法减少光刻次数、节省这项昂贵工艺的成本，到也许我们需要重新思考晶体管。This is a very risk-averse industry for very good reason, for exactly that reason. You put in tens of billions of dollars, and you really don’t want to take any risks. You want to keep doing things the way they’ve been done for literally decades. This is not just true of semiconductors, but everything really. If you’ve just kept on doing that for decade upon decade, you just become indoctrinated. There are engineers who probably work at Intel who are new, who come in and they’re taught, “This is how the fab works, this is the process flow.” They just take that as gospel. That’s just how it is done. But is that really the best way to build a chip today? It’s a really valid question. I’m very curious what you’re hinting at, because it could be anything from figuring out ways to use fewer litho passes and economize on this expensive component, to maybe we need to rethink the transistor.

程度如何——以上皆是。晶体管架构一直在演进。单是硅晶体管，过去三四十年来就持续发展，而且这种趋势还会延续。我们已经看到晶体管从平面结构发展到 FinFET，再到如今的全环绕栅极晶体管。未来还会有更多变化。这条技术路线图已经存在，而且界定得相当清晰，许多人都在为此努力。但还有一些问题，比如……如今真的还需要洁净室吗？我们真的需要像现在这样复杂、精密的基础设施吗？肯定可以做个实验：让人们在研究晶圆厂里一边吃汉堡、一边抽雪茄，然后看看良率会怎样。这会是个很棒的实验，但没有哪家现有厂商——英特尔、台积电或三星——会愿意主动这么做。这就是我的意思。What is the level of— All of the above. Transistor architecture is evolving. Just the silicon transistor has continued to evolve over 30, 40 years, and that will continue. You’ve seen the evolution from the planar transistor to FinFETs to now gate-all-around transistors. There’ll be more. That roadmap exists, it’s pretty well defined, with a lot of people working on it. But there are things like… Do you really need a clean room today? Do you need the infrastructure to be as sophisticated, as complex as it is today? Surely one can run an experiment where you have people eating hamburgers and smoking cigars in the research fab and see what happens to yield. That would be a great experiment to run, but no incumbent — Intel or TSMC or Samsung — would want to willingly do that. That’s what I meant by this.

这是一个极度规避风险的行业，原因很充分。生产力每损失一天……我不知道这相当于多少美元。但如果将来不用建造洁净室，就能省下很多钱。不过，真正的问题还是风险，是对未知的恐惧。没人会愿意主动承担这种风险。这就是为什么我觉得，有时候从零开始、重新审视一切是件好事。顺便说一句，芯片设计也是如此。我们设计 CPU 的许多方法，可能在 30 年前就已经定型了。这是否意味着继续沿用同样的方法是明智的？恐怕不是。但这是个非常复杂的问题。在芯片设计领域，我想人们承担风险的意愿或许更高一些；而这个领域则没那么高。不过，考虑到如今的经济状况，我认为这个问题非常值得探讨。也许有更聪明的做法。It’s a very risk-averse business, for good reason. Every one day lost in productivity is… I don’t know how many dollars. But you save so much money in not having to build clean rooms in the future. But it’s really the risk, the fear of the unknown. Nobody is going to willingly take that risk. That’s why I think sometimes it’s good to just start with a clean slate and rethink everything. The same thing applies to chip design, by the way. Many of the ways we do CPU design were probably locked in 30 years ago. Does that mean it’s smart to still do it the same way? Probably not. But this is a very complex problem. In chip design, I guess the capacity to take risk is maybe higher. This one, less so. But given where the economics is today, I think it’s a very valid question to ask. Maybe there’s a smarter way to do this.

最后收尾时，也许我们可以回到采访一开始提出的那个问题：面对即将到来、而且已经到来的这波疯狂的 AI 需求，英特尔会如何应对？听起来，英特尔应该做的——如果最终的瓶颈在于你们已经有了这些晶圆厂，也有能力扩建它们，但最终缺少的会是供应链上游的设备——就是现在尽可能多地筹集资金。就像英伟达已经锁定了内存和其他组件，据称为此作出了价值数千亿美元的承诺一样，英特尔或许也应该这么做：作出所有这些承诺，这样在未来几年，美国就能处于有利位置，在这里实现大部分最先进水平的半导体制造。To close out, maybe we’ll start off at the same question we began the interview with, which is, how does Intel respond to this crazy AI demand that’s incoming and has already arrived? It sounds like what Intel ought to do — if the ultimate bottleneck is that you guys already have these foundries, you already have the ability to expand these foundries, but what you will eventually lack is the tools from upstream in the supply chain — is to just raise as much capital as possible right now. The same way that Nvidia has locked down memory and other components for reportedly hundreds of billions of dollars worth of commitments that it’s made, Intel should maybe do the same thing: make all these commitments so that over the coming years, the US is in good position to have the bulk of semiconductor manufacturing at the most advanced levels happening here.

你的意思是，我们应该多买很多工具，对吧？是的，因为听起来，要不然过几年你可能就会觉得：“天哪，我们现在本来可以赚数万亿美元，可所有工具都在台湾。”是的，这是个非常合理的问题。如果当时我们就知道现在知道的这些，一年前我们就会加大投资。既然现在已经了解了这些，我想我们会加大投资。You’re suggesting we should be buying a lot more tools, right? Yeah, because it sounds like otherwise in a couple years you’d just be in a position where you’re like, “Oh man, we could be making trillions of dollars right now, but all the tools are in Taiwan.” Yes, that’s a very valid question. Had we known what we know today, we would have invested more like a year ago. Knowing what we know now, I think we’ll be investing more.